17fd09c021
There are several new L1D cache flush bits added to the hcall which reflect hardware security features for speculative cache access issues. These behaviours are now being specified as negative in order to simplify patched kernel compatibility with older firmware (a new problem found in existing systems would automatically be vulnerable). [dwg: Technically this changes behaviour for existing machine types. After discussion with Nick, we've determined this is safe, because the worst that will happen if a guest gets the wrong information due to a migration is that it will perform some unnecessary workarounds, but will remain correct and secure (well, as secure as it was going to be anyway). In addition the change only affects cap-cfpc=safe which is not enabled by default, and in fact is not possible to set on any current hardware (though it's expected it will be possible on POWER10)] Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20210615044107.1481608-1-npiggin@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> |
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fdt.h | ||
mac_dbdma.h | ||
openpic_kvm.h | ||
openpic.h | ||
pef.h | ||
pnv_core.h | ||
pnv_homer.h | ||
pnv_lpc.h | ||
pnv_occ.h | ||
pnv_pnor.h | ||
pnv_psi.h | ||
pnv_xive.h | ||
pnv_xscom.h | ||
pnv.h | ||
ppc4xx.h | ||
ppc_e500.h | ||
ppc.h | ||
spapr_cpu_core.h | ||
spapr_drc.h | ||
spapr_irq.h | ||
spapr_numa.h | ||
spapr_nvdimm.h | ||
spapr_ovec.h | ||
spapr_rtas.h | ||
spapr_tpm_proxy.h | ||
spapr_vio.h | ||
spapr_xive.h | ||
spapr.h | ||
vof.h | ||
xics_spapr.h | ||
xics.h | ||
xive_regs.h | ||
xive.h |