qemu/hw/riscv
Bin Meng 17aad9f276 hw/riscv: sifive_u: Support different boot source per MSEL pin state
SiFive FU540 SoC supports booting from several sources, which are
controlled using the Mode Select (MSEL[3:0]) pins on the chip.
Typically, the boot process runs through several stages before it
begins execution of user-provided programs.

The SoC supports booting from memory-mapped QSPI flash, which is
how start_in_flash property is used for at present. This matches
MSEL = 1 configuration (QSPI0).

Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL).
It's not necessary for QEMU to implement the full ZSBL ROM codes,
because we know ZSBL downloads the next stage program into the L2
LIM at address 0x8000000 and executes from there. We can bypass
the whole ZSBL execution and use "-bios" to load the next stage
program directly if MSEL indicates a ZSBL booting flow.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-4-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19 08:25:27 -07:00
..
boot.c riscv: Change the default behavior if no -bios option is specified 2020-06-03 09:11:51 -07:00
Kconfig hw/char: Initial commit of Ibex UART 2020-06-19 08:24:07 -07:00
Makefile.objs riscv: Initial commit of OpenTitan machine 2020-06-03 09:11:51 -07:00
opentitan.c hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions 2020-06-19 08:24:07 -07:00
riscv_hart.c qdev: Convert bus-less devices to qdev_realize() with Coccinelle 2020-06-15 22:06:04 +02:00
riscv_htif.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
sifive_clint.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_e_prci.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_e.c hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 2020-06-19 08:25:27 -07:00
sifive_gpio.c hw/riscv: sifive_gpio: Do not blindly trigger output IRQs 2020-06-19 08:25:27 -07:00
sifive_plic.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_test.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_u_otp.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
sifive_u_prci.c riscv: sifive: Implement PRCI model for FU540 2019-09-17 08:42:47 -07:00
sifive_u.c hw/riscv: sifive_u: Support different boot source per MSEL pin state 2020-06-19 08:25:27 -07:00
sifive_uart.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
spike.c sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1 2020-06-15 22:06:04 +02:00
trace-events SiFive RISC-V GPIO Device 2019-05-24 11:58:30 -07:00
virt.c sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1 2020-06-15 22:06:04 +02:00