f1f7e4bf76
The i.MX6 GPIO device supports 2 interrupts instead of one. * 1 for the lower 16 GPIOs. * 1 for the upper 16 GPIOs. i.MX31 and i.MX25 only support 1 interrupt for the 32 GPIOs. So we add a property to turn the behavior on when required. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1447497668-1603-1-git-send-email-jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
/*
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* i.MX processors GPIO registers definition.
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*
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* Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __IMX_GPIO_H_
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#define __IMX_GPIO_H_
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#include <hw/sysbus.h>
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#define TYPE_IMX_GPIO "imx.gpio"
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#define IMX_GPIO(obj) OBJECT_CHECK(IMXGPIOState, (obj), TYPE_IMX_GPIO)
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#define IMX_GPIO_MEM_SIZE 0x20
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/* i.MX GPIO memory map */
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#define DR_ADDR 0x00 /* DATA REGISTER */
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#define GDIR_ADDR 0x04 /* DIRECTION REGISTER */
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#define PSR_ADDR 0x08 /* PAD STATUS REGISTER */
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#define ICR1_ADDR 0x0c /* INTERRUPT CONFIGURATION REGISTER 1 */
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#define ICR2_ADDR 0x10 /* INTERRUPT CONFIGURATION REGISTER 2 */
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#define IMR_ADDR 0x14 /* INTERRUPT MASK REGISTER */
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#define ISR_ADDR 0x18 /* INTERRUPT STATUS REGISTER */
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#define EDGE_SEL_ADDR 0x1c /* EDGE SEL REGISTER */
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#define IMX_GPIO_PIN_COUNT 32
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typedef struct IMXGPIOState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t dr;
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uint32_t gdir;
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uint32_t psr;
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uint64_t icr;
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uint32_t imr;
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uint32_t isr;
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bool has_edge_sel;
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uint32_t edge_sel;
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bool has_upper_pin_irq;
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qemu_irq irq[2];
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qemu_irq output[IMX_GPIO_PIN_COUNT];
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} IMXGPIOState;
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#endif /* __IMX_GPIO_H_ */
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