mirror of https://gitlab.com/qemu-project/qemu
c20a135a7a
In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt into the GICv3CPUState struct's maintenance_irq field. This will only work if the board happens to have already wired up the CPU maintenance IRQ before the GIC was realized. Unfortunately this is not the case for the 'virt' board, and so the value that gets copied is NULL (since a qemu_irq is really a pointer to an IRQState struct under the hood). The effect is that the CPU interface code never actually raises the maintenance interrupt line. Instead, since the GICv3CPUState has a pointer to the CPUState, make the dereference at the point where we want to raise the interrupt, to avoid an implicit requirement on board code to wire things up in a particular order. Reported-by: Jose Martins <josemartins90@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201009153904.28529-1-peter.maydell@linaro.org Reviewed-by: Luc Michel <luc@lmichel.fr> |
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| .. | ||
| allwinner-a10-pic.h | ||
| arm_gic.h | ||
| arm_gic_common.h | ||
| arm_gicv3.h | ||
| arm_gicv3_common.h | ||
| arm_gicv3_its_common.h | ||
| armv7m_nvic.h | ||
| aspeed_vic.h | ||
| bcm2835_ic.h | ||
| bcm2836_control.h | ||
| heathrow_pic.h | ||
| i8259.h | ||
| ibex_plic.h | ||
| imx_avic.h | ||
| imx_gpcv2.h | ||
| intc.h | ||
| mips_gic.h | ||
| realview_gic.h | ||
| rx_icu.h | ||
| sifive_clint.h | ||
| sifive_plic.h | ||
| xlnx-pmu-iomod-intc.h | ||
| xlnx-zynqmp-ipi.h | ||