533 lines
16 KiB
C
533 lines
16 KiB
C
/*
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* ARM Versatile/PB PCI host controller
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*
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* Copyright (c) 2006-2009 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the LGPL.
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*/
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#include "hw/sysbus.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_host.h"
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#include "exec/address-spaces.h"
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/* Old and buggy versions of QEMU used the wrong mapping from
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* PCI IRQs to system interrupt lines. Unfortunately the Linux
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* kernel also had the corresponding bug in setting up interrupts
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* (so older kernels work on QEMU and not on real hardware).
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* We automatically detect these broken kernels and flip back
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* to the broken irq mapping by spotting guest writes to the
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* PCI_INTERRUPT_LINE register to see where the guest thinks
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* interrupts are going to be routed. So we start in state
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* ASSUME_OK on reset, and transition to either BROKEN or
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* FORCE_OK at the first write to an INTERRUPT_LINE register for
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* a slot where broken and correct interrupt mapping would differ.
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* Once in either BROKEN or FORCE_OK we never transition again;
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* this allows a newer kernel to use the INTERRUPT_LINE
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* registers arbitrarily once it has indicated that it isn't
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* broken in its init code somewhere.
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*
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* Unfortunately we have to cope with multiple different
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* variants on the broken kernel behaviour:
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* phase I (before kernel commit 1bc39ac5d) kernels assume old
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* QEMU behaviour, so they use IRQ 27 for all slots
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* phase II (1bc39ac5d and later, but before e3e92a7be6) kernels
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* swizzle IRQs between slots, but do it wrongly, so they
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* work only for every fourth PCI card, and only if (like old
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* QEMU) the PCI host device is at slot 0 rather than where
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* the h/w actually puts it
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* phase III (e3e92a7be6 and later) kernels still swizzle IRQs between
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* slots wrongly, but add a fixed offset of 64 to everything
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* they write to PCI_INTERRUPT_LINE.
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*
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* We live in hope of a mythical phase IV kernel which might
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* actually behave in ways that work on the hardware. Such a
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* kernel should probably start off by writing some value neither
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* 27 nor 91 to slot zero's PCI_INTERRUPT_LINE register to
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* disable the autodetection. After that it can do what it likes.
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*
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* Slot % 4 | hw | I | II | III
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* -------------------------------
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* 0 | 29 | 27 | 27 | 91
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* 1 | 30 | 27 | 28 | 92
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* 2 | 27 | 27 | 29 | 93
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* 3 | 28 | 27 | 30 | 94
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*
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* Since our autodetection is not perfect we also provide a
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* property so the user can make us start in BROKEN or FORCE_OK
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* on reset if they know they have a bad or good kernel.
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*/
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enum {
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PCI_VPB_IRQMAP_ASSUME_OK,
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PCI_VPB_IRQMAP_BROKEN,
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PCI_VPB_IRQMAP_FORCE_OK,
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};
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typedef struct {
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PCIHostState parent_obj;
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qemu_irq irq[4];
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MemoryRegion controlregs;
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MemoryRegion mem_config;
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MemoryRegion mem_config2;
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/* Containers representing the PCI address spaces */
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MemoryRegion pci_io_space;
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MemoryRegion pci_mem_space;
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/* Alias regions into PCI address spaces which we expose as sysbus regions.
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* The offsets into pci_mem_space are controlled by the imap registers.
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*/
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MemoryRegion pci_io_window;
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MemoryRegion pci_mem_window[3];
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PCIBus pci_bus;
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PCIDevice pci_dev;
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/* Constant for life of device: */
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int realview;
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uint32_t mem_win_size[3];
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uint8_t irq_mapping_prop;
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/* Variable state: */
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uint32_t imap[3];
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uint32_t smap[3];
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uint32_t selfid;
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uint32_t flags;
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uint8_t irq_mapping;
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} PCIVPBState;
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static void pci_vpb_update_window(PCIVPBState *s, int i)
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{
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/* Adjust the offset of the alias region we use for
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* the memory window i to account for a change in the
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* value of the corresponding IMAP register.
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* Note that the semantics of the IMAP register differ
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* for realview and versatile variants of the controller.
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*/
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hwaddr offset;
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if (s->realview) {
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/* Top bits of register (masked according to window size) provide
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* top bits of PCI address.
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*/
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offset = s->imap[i] & ~(s->mem_win_size[i] - 1);
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} else {
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/* Bottom 4 bits of register provide top 4 bits of PCI address */
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offset = s->imap[i] << 28;
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}
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memory_region_set_alias_offset(&s->pci_mem_window[i], offset);
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}
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static void pci_vpb_update_all_windows(PCIVPBState *s)
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{
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/* Update all alias windows based on the current register state */
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int i;
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for (i = 0; i < 3; i++) {
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pci_vpb_update_window(s, i);
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}
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}
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static int pci_vpb_post_load(void *opaque, int version_id)
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{
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PCIVPBState *s = opaque;
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pci_vpb_update_all_windows(s);
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return 0;
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}
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static const VMStateDescription pci_vpb_vmstate = {
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.name = "versatile-pci",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pci_vpb_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(imap, PCIVPBState, 3),
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VMSTATE_UINT32_ARRAY(smap, PCIVPBState, 3),
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VMSTATE_UINT32(selfid, PCIVPBState),
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VMSTATE_UINT32(flags, PCIVPBState),
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VMSTATE_UINT8(irq_mapping, PCIVPBState),
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VMSTATE_END_OF_LIST()
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}
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};
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#define TYPE_VERSATILE_PCI "versatile_pci"
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#define PCI_VPB(obj) \
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OBJECT_CHECK(PCIVPBState, (obj), TYPE_VERSATILE_PCI)
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#define TYPE_VERSATILE_PCI_HOST "versatile_pci_host"
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#define PCI_VPB_HOST(obj) \
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OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST)
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typedef enum {
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PCI_IMAP0 = 0x0,
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PCI_IMAP1 = 0x4,
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PCI_IMAP2 = 0x8,
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PCI_SELFID = 0xc,
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PCI_FLAGS = 0x10,
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PCI_SMAP0 = 0x14,
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PCI_SMAP1 = 0x18,
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PCI_SMAP2 = 0x1c,
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} PCIVPBControlRegs;
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static void pci_vpb_reg_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIVPBState *s = opaque;
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switch (addr) {
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case PCI_IMAP0:
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case PCI_IMAP1:
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case PCI_IMAP2:
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{
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int win = (addr - PCI_IMAP0) >> 2;
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s->imap[win] = val;
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pci_vpb_update_window(s, win);
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break;
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}
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case PCI_SELFID:
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s->selfid = val;
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break;
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case PCI_FLAGS:
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s->flags = val;
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break;
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case PCI_SMAP0:
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case PCI_SMAP1:
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case PCI_SMAP2:
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{
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int win = (addr - PCI_SMAP0) >> 2;
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s->smap[win] = val;
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break;
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}
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pci_vpb_reg_write: Bad offset %x\n", (int)addr);
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break;
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}
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}
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static uint64_t pci_vpb_reg_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PCIVPBState *s = opaque;
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switch (addr) {
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case PCI_IMAP0:
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case PCI_IMAP1:
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case PCI_IMAP2:
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{
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int win = (addr - PCI_IMAP0) >> 2;
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return s->imap[win];
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}
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case PCI_SELFID:
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return s->selfid;
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case PCI_FLAGS:
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return s->flags;
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case PCI_SMAP0:
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case PCI_SMAP1:
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case PCI_SMAP2:
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{
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int win = (addr - PCI_SMAP0) >> 2;
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return s->smap[win];
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}
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pci_vpb_reg_read: Bad offset %x\n", (int)addr);
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return 0;
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}
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}
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static const MemoryRegionOps pci_vpb_reg_ops = {
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.read = pci_vpb_reg_read,
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.write = pci_vpb_reg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static int pci_vpb_broken_irq(int slot, int irq)
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{
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/* Determine whether this IRQ value for this slot represents a
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* known broken Linux kernel behaviour for this slot.
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* Return one of the PCI_VPB_IRQMAP_ constants:
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* BROKEN : if this definitely looks like a broken kernel
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* FORCE_OK : if this definitely looks good
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* ASSUME_OK : if we can't tell
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*/
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slot %= PCI_NUM_PINS;
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if (irq == 27) {
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if (slot == 2) {
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/* Might be a Phase I kernel, or might be a fixed kernel,
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* since slot 2 is where we expect this IRQ.
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*/
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return PCI_VPB_IRQMAP_ASSUME_OK;
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}
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/* Phase I kernel */
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return PCI_VPB_IRQMAP_BROKEN;
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}
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if (irq == slot + 27) {
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/* Phase II kernel */
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return PCI_VPB_IRQMAP_BROKEN;
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}
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if (irq == slot + 27 + 64) {
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/* Phase III kernel */
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return PCI_VPB_IRQMAP_BROKEN;
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}
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/* Anything else must be a fixed kernel, possibly using an
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* arbitrary irq map.
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*/
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return PCI_VPB_IRQMAP_FORCE_OK;
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}
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static void pci_vpb_config_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIVPBState *s = opaque;
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if (!s->realview && (addr & 0xff) == PCI_INTERRUPT_LINE
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&& s->irq_mapping == PCI_VPB_IRQMAP_ASSUME_OK) {
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uint8_t devfn = addr >> 8;
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s->irq_mapping = pci_vpb_broken_irq(PCI_SLOT(devfn), val);
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}
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pci_data_write(&s->pci_bus, addr, val, size);
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}
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static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PCIVPBState *s = opaque;
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uint32_t val;
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val = pci_data_read(&s->pci_bus, addr, size);
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return val;
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}
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static const MemoryRegionOps pci_vpb_config_ops = {
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.read = pci_vpb_config_read,
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.write = pci_vpb_config_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
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{
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PCIVPBState *s = container_of(d->bus, PCIVPBState, pci_bus);
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if (s->irq_mapping == PCI_VPB_IRQMAP_BROKEN) {
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/* Legacy broken IRQ mapping for compatibility with old and
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* buggy Linux guests
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*/
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return irq_num;
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}
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/* Slot to IRQ mapping for RealView Platform Baseboard 926 backplane
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* name slot IntA IntB IntC IntD
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* A 31 IRQ28 IRQ29 IRQ30 IRQ27
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* B 30 IRQ27 IRQ28 IRQ29 IRQ30
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* C 29 IRQ30 IRQ27 IRQ28 IRQ29
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* Slot C is for the host bridge; A and B the peripherals.
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* Our output irqs 0..3 correspond to the baseboard's 27..30.
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*
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* This mapping function takes account of an oddity in the PB926
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* board wiring, where the FPGA's P_nINTA input is connected to
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* the INTB connection on the board PCI edge connector, P_nINTB
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* is connected to INTC, and so on, so everything is one number
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* further round from where you might expect.
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*/
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return pci_swizzle_map_irq_fn(d, irq_num + 2);
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}
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static int pci_vpb_rv_map_irq(PCIDevice *d, int irq_num)
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{
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/* Slot to IRQ mapping for RealView EB and PB1176 backplane
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* name slot IntA IntB IntC IntD
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* A 31 IRQ50 IRQ51 IRQ48 IRQ49
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* B 30 IRQ49 IRQ50 IRQ51 IRQ48
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* C 29 IRQ48 IRQ49 IRQ50 IRQ51
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* Slot C is for the host bridge; A and B the peripherals.
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* Our output irqs 0..3 correspond to the baseboard's 48..51.
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*
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* The PB1176 and EB boards don't have the PB926 wiring oddity
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* described above; P_nINTA connects to INTA, P_nINTB to INTB
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* and so on, which is why this mapping function is different.
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*/
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return pci_swizzle_map_irq_fn(d, irq_num + 3);
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}
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static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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qemu_set_irq(pic[irq_num], level);
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}
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static void pci_vpb_reset(DeviceState *d)
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{
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PCIVPBState *s = PCI_VPB(d);
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s->imap[0] = 0;
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s->imap[1] = 0;
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s->imap[2] = 0;
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s->smap[0] = 0;
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s->smap[1] = 0;
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s->smap[2] = 0;
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s->selfid = 0;
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s->flags = 0;
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s->irq_mapping = s->irq_mapping_prop;
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pci_vpb_update_all_windows(s);
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}
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static void pci_vpb_init(Object *obj)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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PCIVPBState *s = PCI_VPB(obj);
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memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 1ULL << 32);
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memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 1ULL << 32);
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pci_bus_new_inplace(&s->pci_bus, DEVICE(obj), "pci",
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&s->pci_mem_space, &s->pci_io_space,
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PCI_DEVFN(11, 0), TYPE_PCI_BUS);
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h->bus = &s->pci_bus;
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object_initialize(&s->pci_dev, TYPE_VERSATILE_PCI_HOST);
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qdev_set_parent_bus(DEVICE(&s->pci_dev), BUS(&s->pci_bus));
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/* Window sizes for VersatilePB; realview_pci's init will override */
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s->mem_win_size[0] = 0x0c000000;
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s->mem_win_size[1] = 0x10000000;
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s->mem_win_size[2] = 0x10000000;
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}
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static void pci_vpb_realize(DeviceState *dev, Error **errp)
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{
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PCIVPBState *s = PCI_VPB(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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pci_map_irq_fn mapfn;
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int i;
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for (i = 0; i < 4; i++) {
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sysbus_init_irq(sbd, &s->irq[i]);
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}
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if (s->realview) {
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mapfn = pci_vpb_rv_map_irq;
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} else {
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mapfn = pci_vpb_map_irq;
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}
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pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4);
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/* Our memory regions are:
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* 0 : our control registers
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* 1 : PCI self config window
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* 2 : PCI config window
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* 3 : PCI IO window
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* 4..6 : PCI memory windows
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*/
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memory_region_init_io(&s->controlregs, OBJECT(s), &pci_vpb_reg_ops, s,
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"pci-vpb-regs", 0x1000);
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sysbus_init_mmio(sbd, &s->controlregs);
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memory_region_init_io(&s->mem_config, OBJECT(s), &pci_vpb_config_ops, s,
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"pci-vpb-selfconfig", 0x1000000);
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sysbus_init_mmio(sbd, &s->mem_config);
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memory_region_init_io(&s->mem_config2, OBJECT(s), &pci_vpb_config_ops, s,
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"pci-vpb-config", 0x1000000);
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sysbus_init_mmio(sbd, &s->mem_config2);
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/* The window into I/O space is always into a fixed base address;
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* its size is the same for both realview and versatile.
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*/
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memory_region_init_alias(&s->pci_io_window, OBJECT(s), "pci-vbp-io-window",
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&s->pci_io_space, 0, 0x100000);
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sysbus_init_mmio(sbd, &s->pci_io_space);
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/* Create the alias regions corresponding to our three windows onto
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* PCI memory space. The sizes vary from board to board; the base
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* offsets are guest controllable via the IMAP registers.
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*/
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for (i = 0; i < 3; i++) {
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memory_region_init_alias(&s->pci_mem_window[i], OBJECT(s), "pci-vbp-window",
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&s->pci_mem_space, 0, s->mem_win_size[i]);
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sysbus_init_mmio(sbd, &s->pci_mem_window[i]);
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}
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/* TODO Remove once realize propagates to child devices. */
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object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
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}
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static int versatile_pci_host_init(PCIDevice *d)
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{
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pci_set_word(d->config + PCI_STATUS,
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PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
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pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
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return 0;
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}
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static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->init = versatile_pci_host_init;
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k->vendor_id = PCI_VENDOR_ID_XILINX;
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k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30;
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k->class_id = PCI_CLASS_PROCESSOR_CO;
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}
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static const TypeInfo versatile_pci_host_info = {
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.name = TYPE_VERSATILE_PCI_HOST,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = versatile_pci_host_class_init,
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};
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|
|
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static Property pci_vpb_properties[] = {
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DEFINE_PROP_UINT8("broken-irq-mapping", PCIVPBState, irq_mapping_prop,
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PCI_VPB_IRQMAP_ASSUME_OK),
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DEFINE_PROP_END_OF_LIST()
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};
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|
|
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static void pci_vpb_class_init(ObjectClass *klass, void *data)
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|
{
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DeviceClass *dc = DEVICE_CLASS(klass);
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|
|
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dc->realize = pci_vpb_realize;
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dc->reset = pci_vpb_reset;
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dc->vmsd = &pci_vpb_vmstate;
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dc->props = pci_vpb_properties;
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}
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|
|
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static const TypeInfo pci_vpb_info = {
|
|
.name = TYPE_VERSATILE_PCI,
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|
.parent = TYPE_PCI_HOST_BRIDGE,
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|
.instance_size = sizeof(PCIVPBState),
|
|
.instance_init = pci_vpb_init,
|
|
.class_init = pci_vpb_class_init,
|
|
};
|
|
|
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static void pci_realview_init(Object *obj)
|
|
{
|
|
PCIVPBState *s = PCI_VPB(obj);
|
|
|
|
s->realview = 1;
|
|
/* The PCI window sizes are different on Realview boards */
|
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s->mem_win_size[0] = 0x01000000;
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|
s->mem_win_size[1] = 0x04000000;
|
|
s->mem_win_size[2] = 0x08000000;
|
|
}
|
|
|
|
static const TypeInfo pci_realview_info = {
|
|
.name = "realview_pci",
|
|
.parent = TYPE_VERSATILE_PCI,
|
|
.instance_init = pci_realview_init,
|
|
};
|
|
|
|
static void versatile_pci_register_types(void)
|
|
{
|
|
type_register_static(&pci_vpb_info);
|
|
type_register_static(&pci_realview_info);
|
|
type_register_static(&versatile_pci_host_info);
|
|
}
|
|
|
|
type_init(versatile_pci_register_types)
|