Leon Schuermann b5fad36452 target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes ... When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP configuration lock bits must not apply. While this behavior is implemented for the pmpcfgX CSRs, this bit is not respected for changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR writes work even on locked regions when the global rule-lock bypass is enabled. Signed-off-by: Leon Schuermann <leons@opentitan.org> Reviewed-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230829215046.1430463-1-leon@is.currently.online> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> (cherry picked from commit 4e3adce124) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>		2023-09-13 12:21:22 +03:00
..
insn_trans	target/riscv: Fix itrigger when icount is used	2023-05-18 21:09:59 +03:00
arch_dump.c	dump: Replace opaque DumpState pointer with a typed one	2022-10-06 19:30:43 +04:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: debug: Introduce tinfo CSR	2022-09-27 11:23:57 +10:00
cpu_helper.c	target/riscv: Honour -semihosting-config userspace=on and enable=on	2022-09-13 17:18:21 +01:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Convert to tcg_ops restore_state_to_opc	2022-10-26 11:11:28 +10:00
cpu.h	dump: Replace opaque DumpState pointer with a typed one	2022-10-06 19:30:43 +04:00
crypto_helper.c
csr.c	target/riscv: debug: Introduce tinfo CSR	2022-09-27 11:23:57 +10:00
debug.c	target/riscv: debug: Add initial support of type 6 trigger	2022-09-27 11:23:57 +10:00
debug.h	target/riscv: debug: Add initial support of type 6 trigger	2022-09-27 11:23:57 +10:00
fpu_helper.c
gdbstub.c	target/riscv: Check the correct exception cause in vector GDB stub	2022-09-27 07:04:38 +10:00
helper.h	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
insn16.decode	target/riscv: fix shifts shamt value for rv128c	2022-09-07 09:18:32 +02:00
insn32.decode	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: rvv: Add mask agnostic for vv instructions	2022-09-07 09:18:32 +02:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c	kvm: Introduce kvm_arch_get_default_type hook	2023-09-11 10:53:50 +03:00
m128_helper.c
machine.c	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	2022-09-27 11:23:57 +10:00
meson.build	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
monitor.c
op_helper.c
pmp.c	target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes	2023-09-13 12:21:22 +03:00
pmp.h
pmu.c	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
pmu.h	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h
time_helper.c	target/riscv: Add vstimecmp support	2022-09-07 09:19:15 +02:00
time_helper.h	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
trace-events
trace.h
translate.c	target/riscv: Set pc_succ_insn for !rvc illegal insn	2023-03-29 10:20:04 +03:00
vector_helper.c	treewide: Remove the unnecessary space before semicolon	2022-10-24 13:41:10 +02:00
XVentanaCondOps.decode