1478b56090
Approach copied from gen_pcie_root_port.c Previously the link defaulted to a maximum of 2.5GT/s and 1x. Enable setting it's maximum values. The actual value after 'training' will depend on the downstream device configuration. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240916173518.1843023-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> |
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| .. | ||
| cxl_downstream.c | ||
| cxl_root_port.c | ||
| cxl_upstream.c | ||
| gen_pcie_root_port.c | ||
| i82801b11.c | ||
| ioh3420.c | ||
| Kconfig | ||
| meson.build | ||
| pci_bridge_dev.c | ||
| pci_expander_bridge_stubs.c | ||
| pci_expander_bridge.c | ||
| pcie_pci_bridge.c | ||
| pcie_root_port.c | ||
| simba.c | ||
| xio3130_downstream.c | ||
| xio3130_upstream.c | ||