qemu/target/xtensa
Max Filippov 13f6a7cd3a target/xtensa: add internal/noop SRs and opcodes
Add two special registers: MMID and DDR:
- MMID is write-only and the only side effect of writing to it is output
  to the trace port, which is not emulated;
- DDR is only accessible in debug mode, which is not emulated.

Add two debug-mode-only opcodes:
- rfdd and rfdo do return from the debug mode, which is not emulated.

Add three internal opcodes for full MMU:
- hwwdtlba and hwwitlba are the internal opcodes that write a value into
  autoupdate DTLB or ITLB entry.
- ldpte is internal opcode that loads PTE entry that covers the most
  recent page fault address.
None of these three opcodes may appear in a valid instruction.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09 09:55:39 -08:00
..
core-dc232b target/xtensa: switch dc232b to libisa 2017-12-18 21:26:19 -08:00
core-dc233c target/xtensa: switch dc233c to libisa 2017-12-18 21:26:19 -08:00
core-fsf target/xtensa: switch fsf to libisa 2017-12-18 21:26:19 -08:00
core-dc232b.c target/xtensa: switch dc232b to libisa 2017-12-18 21:26:19 -08:00
core-dc233c.c target/xtensa: switch dc233c to libisa 2017-12-18 21:26:19 -08:00
core-fsf.c target/xtensa: switch fsf to libisa 2017-12-18 21:26:19 -08:00
cpu-qom.h
cpu.c xtensa: cleanup cpu type name composition 2017-10-27 16:04:27 +02:00
cpu.h target/xtensa: add internal/noop SRs and opcodes 2018-01-09 09:55:39 -08:00
gdbstub.c target/xtensa: gdbstub: drop dead return statement 2017-07-11 11:18:37 +03:00
helper.c target/xtensa: use libisa for instruction decoding 2018-01-09 09:55:38 -08:00
helper.h target/xtensa updates: 2017-01-25 16:36:57 +00:00
import_core.sh target/xtensa: update import_core.sh script for libisa 2017-12-18 21:26:19 -08:00
Makefile.objs target/xtensa: import libisa source 2017-12-18 21:26:19 -08:00
monitor.c monitor: Fix crashes when using HMP commands without CPU 2017-02-21 18:29:01 +00:00
op_helper.c target/xtensa: pass actual frame size to the entry helper 2017-12-18 21:26:18 -08:00
overlay_tool.h target/xtensa: sim: instantiate local memories 2017-02-23 10:30:41 -08:00
translate.c target/xtensa: add internal/noop SRs and opcodes 2018-01-09 09:55:39 -08:00
xtensa-isa-internal.h target/xtensa: import libisa source 2017-12-18 21:26:19 -08:00
xtensa-isa.c target/xtensa: import libisa source 2017-12-18 21:26:19 -08:00
xtensa-isa.h target/xtensa: import libisa source 2017-12-18 21:26:19 -08:00
xtensa-semi.c char: add backend hotswap handler 2017-07-14 11:04:33 +02:00