13b55754af
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@252 c046a42c-6fe2-441c-8c8c-71466251a162
267 lines
6.8 KiB
C
267 lines
6.8 KiB
C
/*
|
|
* i386 virtual CPU header
|
|
*
|
|
* Copyright (c) 2003 Fabrice Bellard
|
|
*
|
|
* This library is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
* License as published by the Free Software Foundation; either
|
|
* version 2 of the License, or (at your option) any later version.
|
|
*
|
|
* This library is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* Lesser General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
* License along with this library; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
*/
|
|
#ifndef CPU_I386_H
|
|
#define CPU_I386_H
|
|
|
|
#include "config.h"
|
|
#include <setjmp.h>
|
|
|
|
#define R_EAX 0
|
|
#define R_ECX 1
|
|
#define R_EDX 2
|
|
#define R_EBX 3
|
|
#define R_ESP 4
|
|
#define R_EBP 5
|
|
#define R_ESI 6
|
|
#define R_EDI 7
|
|
|
|
#define R_AL 0
|
|
#define R_CL 1
|
|
#define R_DL 2
|
|
#define R_BL 3
|
|
#define R_AH 4
|
|
#define R_CH 5
|
|
#define R_DH 6
|
|
#define R_BH 7
|
|
|
|
#define R_ES 0
|
|
#define R_CS 1
|
|
#define R_SS 2
|
|
#define R_DS 3
|
|
#define R_FS 4
|
|
#define R_GS 5
|
|
|
|
/* segment descriptor fields */
|
|
#define DESC_G_MASK (1 << 23)
|
|
#define DESC_B_MASK (1 << 22)
|
|
#define DESC_AVL_MASK (1 << 20)
|
|
#define DESC_P_MASK (1 << 15)
|
|
#define DESC_DPL_SHIFT 13
|
|
#define DESC_S_MASK (1 << 12)
|
|
#define DESC_TYPE_SHIFT 8
|
|
#define DESC_A_MASK (1 << 8)
|
|
|
|
#define DESC_CS_MASK (1 << 11)
|
|
#define DESC_C_MASK (1 << 10)
|
|
#define DESC_R_MASK (1 << 9)
|
|
|
|
#define DESC_E_MASK (1 << 10)
|
|
#define DESC_W_MASK (1 << 9)
|
|
|
|
/* eflags masks */
|
|
#define CC_C 0x0001
|
|
#define CC_P 0x0004
|
|
#define CC_A 0x0010
|
|
#define CC_Z 0x0040
|
|
#define CC_S 0x0080
|
|
#define CC_O 0x0800
|
|
|
|
#define TF_MASK 0x00000100
|
|
#define IF_MASK 0x00000200
|
|
#define DF_MASK 0x00000400
|
|
#define IOPL_MASK 0x00003000
|
|
#define NT_MASK 0x00004000
|
|
#define RF_MASK 0x00010000
|
|
#define VM_MASK 0x00020000
|
|
#define AC_MASK 0x00040000
|
|
#define VIF_MASK 0x00080000
|
|
#define VIP_MASK 0x00100000
|
|
#define ID_MASK 0x00200000
|
|
|
|
#define CR0_PE_MASK (1 << 0)
|
|
#define CR0_TS_MASK (1 << 3)
|
|
#define CR0_WP_MASK (1 << 16)
|
|
#define CR0_AM_MASK (1 << 18)
|
|
#define CR0_PG_MASK (1 << 31)
|
|
|
|
#define CR4_VME_MASK (1 << 0)
|
|
#define CR4_PVI_MASK (1 << 1)
|
|
#define CR4_TSD_MASK (1 << 2)
|
|
#define CR4_DE_MASK (1 << 3)
|
|
|
|
#define EXCP00_DIVZ 0
|
|
#define EXCP01_SSTP 1
|
|
#define EXCP02_NMI 2
|
|
#define EXCP03_INT3 3
|
|
#define EXCP04_INTO 4
|
|
#define EXCP05_BOUND 5
|
|
#define EXCP06_ILLOP 6
|
|
#define EXCP07_PREX 7
|
|
#define EXCP08_DBLE 8
|
|
#define EXCP09_XERR 9
|
|
#define EXCP0A_TSS 10
|
|
#define EXCP0B_NOSEG 11
|
|
#define EXCP0C_STACK 12
|
|
#define EXCP0D_GPF 13
|
|
#define EXCP0E_PAGE 14
|
|
#define EXCP10_COPR 16
|
|
#define EXCP11_ALGN 17
|
|
#define EXCP12_MCHK 18
|
|
|
|
#define EXCP_INTERRUPT 256 /* async interruption */
|
|
|
|
enum {
|
|
CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
|
|
CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
|
|
CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
|
|
|
|
CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
|
CC_OP_ADDW,
|
|
CC_OP_ADDL,
|
|
|
|
CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
|
CC_OP_ADCW,
|
|
CC_OP_ADCL,
|
|
|
|
CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
|
CC_OP_SUBW,
|
|
CC_OP_SUBL,
|
|
|
|
CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
|
|
CC_OP_SBBW,
|
|
CC_OP_SBBL,
|
|
|
|
CC_OP_LOGICB, /* modify all flags, CC_DST = res */
|
|
CC_OP_LOGICW,
|
|
CC_OP_LOGICL,
|
|
|
|
CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
|
CC_OP_INCW,
|
|
CC_OP_INCL,
|
|
|
|
CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
|
|
CC_OP_DECW,
|
|
CC_OP_DECL,
|
|
|
|
CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
|
|
CC_OP_SHLW,
|
|
CC_OP_SHLL,
|
|
|
|
CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
|
|
CC_OP_SARW,
|
|
CC_OP_SARL,
|
|
|
|
CC_OP_NB,
|
|
};
|
|
|
|
#ifdef __i386__
|
|
#define USE_X86LDOUBLE
|
|
#endif
|
|
|
|
#ifdef USE_X86LDOUBLE
|
|
typedef long double CPU86_LDouble;
|
|
#else
|
|
typedef double CPU86_LDouble;
|
|
#endif
|
|
|
|
typedef struct SegmentCache {
|
|
uint32_t selector;
|
|
uint8_t *base;
|
|
unsigned long limit;
|
|
uint8_t seg_32bit;
|
|
} SegmentCache;
|
|
|
|
typedef struct CPUX86State {
|
|
/* standard registers */
|
|
uint32_t regs[8];
|
|
uint32_t eip;
|
|
uint32_t eflags; /* eflags register. During CPU emulation, CC
|
|
flags and DF are set to zero because they are
|
|
stored elsewhere */
|
|
|
|
/* emulator internal eflags handling */
|
|
uint32_t cc_src;
|
|
uint32_t cc_dst;
|
|
uint32_t cc_op;
|
|
int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
|
|
|
|
/* FPU state */
|
|
unsigned int fpstt; /* top of stack index */
|
|
unsigned int fpus;
|
|
unsigned int fpuc;
|
|
uint8_t fptags[8]; /* 0 = valid, 1 = empty */
|
|
CPU86_LDouble fpregs[8];
|
|
|
|
/* emulator internal variables */
|
|
CPU86_LDouble ft0;
|
|
union {
|
|
float f;
|
|
double d;
|
|
int i32;
|
|
int64_t i64;
|
|
} fp_convert;
|
|
|
|
/* segments */
|
|
SegmentCache segs[6]; /* selector values */
|
|
SegmentCache ldt;
|
|
SegmentCache tr;
|
|
SegmentCache gdt; /* only base and limit are used */
|
|
SegmentCache idt; /* only base and limit are used */
|
|
|
|
/* exception/interrupt handling */
|
|
jmp_buf jmp_env;
|
|
int exception_index;
|
|
int error_code;
|
|
uint32_t cr[5]; /* NOTE: cr1 is unused */
|
|
uint32_t dr[8]; /* debug registers */
|
|
int interrupt_request;
|
|
|
|
/* user data */
|
|
void *opaque;
|
|
} CPUX86State;
|
|
|
|
#ifndef IN_OP_I386
|
|
void cpu_x86_outb(CPUX86State *env, int addr, int val);
|
|
void cpu_x86_outw(CPUX86State *env, int addr, int val);
|
|
void cpu_x86_outl(CPUX86State *env, int addr, int val);
|
|
int cpu_x86_inb(CPUX86State *env, int addr);
|
|
int cpu_x86_inw(CPUX86State *env, int addr);
|
|
int cpu_x86_inl(CPUX86State *env, int addr);
|
|
#endif
|
|
|
|
CPUX86State *cpu_x86_init(void);
|
|
int cpu_x86_exec(CPUX86State *s);
|
|
void cpu_x86_interrupt(CPUX86State *s);
|
|
void cpu_x86_close(CPUX86State *s);
|
|
|
|
/* needed to load some predefinied segment registers */
|
|
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
|
|
|
|
/* simulate fsave/frstor */
|
|
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
|
|
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
|
|
|
|
/* you can call this signal handler from your SIGBUS and SIGSEGV
|
|
signal handlers to inform the virtual CPU of exceptions. non zero
|
|
is returned if the signal was handled by the virtual CPU. */
|
|
struct siginfo;
|
|
int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc);
|
|
|
|
/* used to debug */
|
|
#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
|
|
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
|
|
void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
|
|
|
|
#define TARGET_PAGE_BITS 12
|
|
#include "cpu-all.h"
|
|
|
|
#endif /* CPU_I386_H */
|