7cf9345c95
Imported from the Hexagon architecture library
imported/macros.def
The macro definitions specify instruction attributes that are applied
to each instruction that references the macro. The generator will
recursively apply attributes to each instruction that used the macro.
imported/allidefs.def
Top level instruction definition file
imported/*.idef
Instruction definition files
These files are input to the first phase of the generator
(gen_semantics.c) to create a python include file with the
instruction semantics and attributes. The python include
file is fed to the second phase to generate various header files.
imported/encode*.def
Instruction encoding bit patterns for every instruction
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1612763186-18161-19-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
69 lines
2.7 KiB
Plaintext
69 lines
2.7 KiB
Plaintext
/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* System Interface Instructions
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*/
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/********************************************/
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/* User->OS interface */
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/********************************************/
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Q6INSN(J2_trap0,"trap0(#u8)",ATTRIBS(A_COF),
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"Trap to Operating System",
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fTRAP(0,uiV);
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)
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Q6INSN(J2_pause,"pause(#u8)",ATTRIBS(A_COF),
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"Enter low-power state for #u8 cycles",{fPAUSE(uiV);})
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Q6INSN(Y2_icinva,"icinva(Rs32)",ATTRIBS(A_ICOP,A_ICFLUSHOP),"Instruction Cache Invalidate Address",{fEA_REG(RsV); fICINVA(EA);})
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Q6INSN(Y2_isync,"isync",ATTRIBS(),"Memory Synchronization",{fISYNC();})
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Q6INSN(Y2_barrier,"barrier",ATTRIBS(A_RESTRICT_SLOT0ONLY),"Memory Barrier",{fBARRIER();})
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Q6INSN(Y2_syncht,"syncht",ATTRIBS(A_RESTRICT_SLOT0ONLY),"Memory Synchronization",{fSYNCH();})
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Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);})
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Q6INSN(Y2_dczeroa,"dczeroa(Rs32)",ATTRIBS(A_STORE,A_RESTRICT_SLOT0ONLY,A_DCZEROA),"Zero an aligned 32-byte cacheline",{fEA_REG(RsV); fDCZEROA(EA);})
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Q6INSN(Y2_dccleana,"dccleana(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean Address",{fEA_REG(RsV); fDCCLEANA(EA);})
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Q6INSN(Y2_dccleaninva,"dccleaninva(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean and Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);})
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Q6INSN(Y2_dcinva,"dcinva(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);})
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Q6INSN(Y4_l2fetch,"l2fetch(Rs32,Rt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
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{ fL2FETCH(RsV,
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(RtV&0xff), /*height*/
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((RtV>>8)&0xff), /*width*/
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((RtV>>16)&0xffff), /*stride*/
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0); /*extra attrib flags*/
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})
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Q6INSN(Y5_l2fetch,"l2fetch(Rs32,Rtt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
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{ fL2FETCH(RsV,
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fGETUHALF(0,RttV), /*height*/
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fGETUHALF(1,RttV), /*width*/
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fGETUHALF(2,RttV), /*stride*/
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fGETUHALF(3,RttV)); /*flags*/
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})
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