7d3912f54e
In the PL022, register offset 0x20 is the ICR, a write-only interrupt-clear register. Register offset 0x24 is DMACR, the DMA control register. We were incorrectly implementing (a stub version of) DMACR at 0x20, and not implementing anything at 0x24. Fix this bug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-21-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
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| .. | ||
| aspeed_smc.c | ||
| imx_spi.c | ||
| Makefile.objs | ||
| mss-spi.c | ||
| omap_spi.c | ||
| pl022.c | ||
| ssi.c | ||
| stm32f2xx_spi.c | ||
| xilinx_spi.c | ||
| xilinx_spips.c | ||