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Max Filippov 4be4c5b826 tests/tcg/xtensa: fix vectors and checks in timer test 
Timer test assumes that timer 0 IRQ has level 1 and other timers have
higher level IRQs. This assumption is not correct and the levels may be
arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and
using it for vector selection and by making the check for the timer
exception cause conditional.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06 15:27:40 -07:00
..
crt.S
tests/tcg/xtensa: fix build for cores without windowed registers
2022-05-06 15:27:40 -07:00
fpu.h
tests/tcg/xtensa: update test_fp0_arith for DFPU
2020-08-21 12:48:15 -07:00
linker.ld.S
…
macros.inc
tests/tcg/xtensa: fix test execution on ISS
2020-08-21 12:48:15 -07:00
Makefile.softmmu-target
Replace TARGET_WORDS_BIGENDIAN
2022-04-06 10:50:37 +02:00
test_b.S
…
test_bi.S
…
test_boolean.S
…
test_break.S
tests/tcg/xtensa: fix watchpoint test
2022-05-06 15:27:40 -07:00
test_bz.S
…
test_cache.S
tests/tcg/xtensa: conditionalize cache option tests
2019-02-28 04:43:23 -08:00
test_clamps.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_dfp0_arith.S
tests/tcg/xtensa: add DFP0 arithmetic tests
2020-08-21 12:48:16 -07:00
test_exclusive.S
target/xtensa: implement exclusive access option
2019-05-15 10:31:52 -07:00
test_extui.S
…
test_flix.S
target/xtensa: fix break_dependency for repeated resources
2019-03-21 21:47:50 -07:00
test_fp0_arith.S
tests/tcg/xtensa: expand madd tests
2020-08-21 12:48:15 -07:00
test_fp0_conv.S
tests/tcg/xtensa: update test_fp0_conv for DFPU
2020-08-21 12:48:16 -07:00
test_fp0_div.S
tests/tcg/xtensa: add fp0 div and sqrt tests
2020-08-21 12:48:16 -07:00
test_fp0_sqrt.S
tests/tcg/xtensa: add fp0 div and sqrt tests
2020-08-21 12:48:16 -07:00
test_fp1.S
tests/tcg/xtensa: update test_fp1 for DFPU
2020-08-21 12:48:16 -07:00
test_fp_cpenable.S
tests/tcg/xtensa: add FPU2000 coprocessor tests
2019-02-28 04:43:24 -08:00
test_interrupt.S
tests/tcg/xtensa: conditionalize interrupt tests
2019-02-28 04:43:23 -08:00
test_load_store.S
target/xtensa: clean up unaligned access
2021-05-20 13:02:58 -07:00
test_loop.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_lsc.S
tests/tcg/xtensa: test double precision load/store
2020-08-21 12:48:16 -07:00
test_mac16.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_max.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_min.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_mmu.S
tests/tcg/xtensa: enable mmu tests for MMUv3
2022-05-06 15:27:40 -07:00
test_mul16.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_mul32.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_nsa.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_phys_mem.S
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
2022-05-06 15:27:40 -07:00
test_quo.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_rem.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_rst0.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_s32c1i.S
tests/tcg/xtensa: conditionalize and fix s32c1i tests
2019-02-28 04:43:23 -08:00
test_sar.S
…
test_sext.S
tests/tcg/xtensa: add straightforward conditionals
2019-02-28 04:43:23 -08:00
test_shift.S
…
test_sr.S
tests/tcg/xtensa: restore vecbase SR after test
2022-05-06 15:27:40 -07:00
test_timer.S
tests/tcg/xtensa: fix vectors and checks in timer test
2022-05-06 15:27:40 -07:00
test_windowed.S
tests/tcg/xtensa: conditionalize windowed register tests
2019-02-28 04:43:23 -08:00
vectors.S
…