0fbf50b6ec
This reverts commit a53ae8e934.
The patch being reverted introduced a low-priority memory region
covering all 64 bit pci address space. This exposed the following bugs
elsewhere in the code:
1. Some memory regions have INT64_MAX size, where the
intent was all 64 bit address space.
This results in a sub-page region, should be UINT64_MAX.
2. page table rendering in exec.c ignores physical address bits
above TARGET_PHYS_ADDR_SPACE_BITS.
Access outside this range (e.g. from device DMA, or gdb stub)
ends up with a wrong region. Registering a region outside this
range leads to page table corruption.
3. Some regions overlap PCI hole and have same priority.
This only works as long as no device uses the overlapping address.
It doesn't look like we can resolve all issues in time for 1.7.
Let's fix the bugs first and apply afterwards for 1.8.
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
#ifndef QEMU_PCI_BUS_H
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#define QEMU_PCI_BUS_H
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/*
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* PCI Bus and Bridge datastructures.
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*
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* Do not access the following members directly;
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* use accessor functions in pci.h, pci_bridge.h
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*/
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struct PCIBus {
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BusState qbus;
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PCIIOMMUFunc iommu_fn;
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void *iommu_opaque;
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uint8_t devfn_min;
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pci_set_irq_fn set_irq;
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pci_map_irq_fn map_irq;
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pci_route_irq_fn route_intx_to_irq;
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pci_hotplug_fn hotplug;
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DeviceState *hotplug_qdev;
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void *irq_opaque;
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PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
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PCIDevice *parent_dev;
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MemoryRegion *address_space_mem;
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MemoryRegion *address_space_io;
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QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
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QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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};
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typedef struct PCIBridgeWindows PCIBridgeWindows;
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/*
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* Aliases for each of the address space windows that the bridge
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* can forward. Mapped into the bridge's parent's address space,
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* as subregions.
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*/
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struct PCIBridgeWindows {
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MemoryRegion alias_pref_mem;
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MemoryRegion alias_mem;
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MemoryRegion alias_io;
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/*
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* When bridge control VGA forwarding is enabled, bridges will
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* provide positive decode on the PCI VGA defined I/O port and
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* MMIO ranges. When enabled forwarding is only qualified on the
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* I/O and memory enable bits in the bridge command register.
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*/
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MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS];
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};
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#define TYPE_PCI_BRIDGE "base-pci-bridge"
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#define PCI_BRIDGE(obj) OBJECT_CHECK(PCIBridge, (obj), TYPE_PCI_BRIDGE)
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struct PCIBridge {
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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/* private member */
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PCIBus sec_bus;
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/*
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* Memory regions for the bridge's address spaces. These regions are not
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* directly added to system_memory/system_io or its descendants.
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* Bridge's secondary bus points to these, so that devices
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* under the bridge see these regions as its address spaces.
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* The regions are as large as the entire address space -
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* they don't take into account any windows.
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*/
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MemoryRegion address_space_mem;
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MemoryRegion address_space_io;
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PCIBridgeWindows *windows;
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pci_map_irq_fn map_irq;
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const char *bus_name;
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};
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#endif /* QEMU_PCI_BUS_H */
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