127ba8d03e
The EBC is shared between 405 and 440 so move it to shared file. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <10eae70509ca4bd74858fc2c0a0f0e4eb9330199.1660746880.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
113 lines
3.4 KiB
C
113 lines
3.4 KiB
C
/*
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* QEMU PowerPC 4xx emulation shared definitions
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef PPC4XX_H
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#define PPC4XX_H
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#include "hw/ppc/ppc.h"
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#include "exec/memory.h"
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#include "hw/sysbus.h"
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void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
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MemoryRegion ram_memories[],
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hwaddr ram_bases[], hwaddr ram_sizes[],
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const ram_addr_t sdram_bank_sizes[]);
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void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
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MemoryRegion ram_memories[],
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hwaddr *ram_bases,
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hwaddr *ram_sizes,
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int do_init);
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#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
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/*
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* Generic DCR device
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*/
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#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
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struct Ppc4xxDcrDeviceState {
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SysBusDevice parent_obj;
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PowerPCCPU *cpu;
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};
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void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
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dcr_read_cb dcr_read, dcr_write_cb dcr_write);
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bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
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Error **errp);
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/* Memory Access Layer (MAL) */
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#define TYPE_PPC4xx_MAL "ppc4xx-mal"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
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struct Ppc4xxMalState {
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Ppc4xxDcrDeviceState parent_obj;
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qemu_irq irqs[4];
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uint32_t cfg;
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uint32_t esr;
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uint32_t ier;
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uint32_t txcasr;
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uint32_t txcarr;
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uint32_t txeobisr;
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uint32_t txdeir;
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uint32_t rxcasr;
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uint32_t rxcarr;
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uint32_t rxeobisr;
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uint32_t rxdeir;
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uint32_t *txctpr;
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uint32_t *rxctpr;
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uint32_t *rcbs;
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uint8_t txcnum;
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uint8_t rxcnum;
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};
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/* Peripheral local bus arbitrer */
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#define TYPE_PPC4xx_PLB "ppc4xx-plb"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB);
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struct Ppc4xxPlbState {
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Ppc4xxDcrDeviceState parent_obj;
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uint32_t acr;
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uint32_t bear;
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uint32_t besr;
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};
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/* Peripheral controller */
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#define TYPE_PPC405_EBC "ppc405-ebc"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
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struct Ppc405EbcState {
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Ppc4xxDcrDeviceState parent_obj;
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uint32_t addr;
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uint32_t bcr[8];
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uint32_t bap[8];
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uint32_t bear;
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uint32_t besr0;
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uint32_t besr1;
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uint32_t cfg;
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};
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#endif /* PPC4XX_H */
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