Richard Henderson 127b2b0863 target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 ...

This is part of a reorganization to the set of mmu_idx.
The EL3 regime only has a single stage translation, and
is always secure.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2020-02-07 14:04:23 +00:00

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alpha

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arm

target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3

2020-02-07 14:04:23 +00:00

cris

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hppa

target/hppa: Allow, but diagnose, LDCW aligned only mod 4

2020-01-27 10:49:51 -08:00

i386

target/i386: Add the 'model-id' for Skylake -v3 CPU models

2020-01-24 20:59:17 +01:00

lm32

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m68k

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microblaze

qdev: set properties with device_class_set_props()

2020-01-24 20:59:15 +01:00

mips

target/mips: Separate FPU-related helpers into their own file

2020-02-04 08:53:54 +01:00

moxie

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nios2

qdev: set properties with device_class_set_props()

2020-01-24 20:59:15 +01:00

openrisc

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ppc

target/ppc: Use probe_write for DCBZ

2020-02-03 11:33:11 +11:00

riscv

* Register qdev properties as class properties (Marc-André)

2020-01-27 09:44:04 +00:00

s390x

s390x: sigp: Fix sense running reporting

2020-01-27 12:13:10 +01:00

sh4

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sparc

qdev: set properties with device_class_set_props()

2020-01-24 20:59:15 +01:00

tilegx

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tricore

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unicore32

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xtensa

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