Anup Patel 31e6d70485 hw/riscv/spike: Allow more than one CPUs ... Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200427080644.168461-4-anup.patel@wdc.com Message-Id: <20200427080644.168461-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-04-29 13:16:38 -07:00
..
boot.c	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	2020-04-29 13:16:38 -07:00
Kconfig
Makefile.objs
riscv_hart.c
riscv_htif.c
sifive_clint.c
sifive_e_prci.c
sifive_e.c
sifive_gpio.c
sifive_plic.c
sifive_test.c
sifive_u_otp.c
sifive_u_prci.c
sifive_u.c	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	2020-04-29 13:16:38 -07:00
sifive_uart.c
spike.c	hw/riscv/spike: Allow more than one CPUs	2020-04-29 13:16:38 -07:00
trace-events
virt.c	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	2020-04-29 13:16:38 -07:00