qemu/include/hw/riscv
Alex Bennée c65d7080d8 hw/riscv: migrate fdt field to generic MachineState
This is a mechanical change to make the fdt available through
MachineState.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210303173642.3805-3-alex.bennee@linaro.org>
2021-03-10 15:34:11 +00:00
..
boot_opensbi.h
boot.h
microchip_pfsoc.h
numa.h
opentitan.h
riscv_hart.h
sifive_cpu.h
sifive_e.h
sifive_u.h hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value 2021-03-04 09:43:29 -05:00
spike.h
virt.h hw/riscv: migrate fdt field to generic MachineState 2021-03-10 15:34:11 +00:00