Stefan Pejic f1663114df target/mips: Add missing default cases for some nanoMIPS pools ... Switch statements for the code segments that handle nanoMIPS instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS do not have proper default case, resulting in not generating reserved instruction exception for certain illegal opcodes. Fix this by adding default cases for these switch statements that trigger reserved instruction exception. Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504110403.613168-7-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>		2022-06-11 11:36:01 +02:00
..
sysemu
tcg	target/mips: Add missing default cases for some nanoMIPS pools	2022-06-11 11:36:01 +02:00
cpu-defs.c.inc	target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU	2021-11-02 14:32:32 +01:00
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu-qom.h	target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro	2022-03-06 22:23:09 +01:00
cpu.c	target/mips: Fix WatchHi.M handling	2022-06-11 11:34:12 +02:00
cpu.h	target/mips: Fix emulation of nanoMIPS BPOSGE32C instruction	2022-06-11 11:35:40 +02:00
fpu_helper.h
fpu.c
gdbstub.c
helper.h
internal.h	MIPS patches queue	2022-03-09 09:13:39 +00:00
Kconfig
kvm_mips.h
kvm.c	Remove qemu-common.h include from most units	2022-04-06 14:31:55 +02:00
meson.build
mips-defs.h
msa.c