qemu/target
Peter Maydell ac179ffe7e target/arm: Set IL bit for pauth, SVE access, BTI trap syndromes
The syndrome register value always has an IL field at bit 25, which
is 0 for a trap on a 16 bit instruction, and 1 for a trap on a 32
bit instruction (or for exceptions which aren't traps on a known
instruction, like PC alignment faults). This means that our
syn_*() functions should always either take an is_16bit argument to
determine whether to set the IL bit, or else unconditionally set it.

We missed setting the IL bit for the syndrome for three kinds of trap:
 * an SVE access exception
 * a pointer authentication check failure
 * a BTI (branch target identification) check failure

All of these traps are AArch64 only, and so the instruction causing
the trap is always 64 bit. This means we can unconditionally set
the IL bit in the syn_*() function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231120150121.3458408-1-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 11a3c4a286)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-12-05 12:32:56 +03:00
..
alpha accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
arm target/arm: Set IL bit for pauth, SVE access, BTI trap syndromes 2023-12-05 12:32:56 +03:00
avr target/avr: Convert to tcg_ops restore_state_to_opc 2022-10-26 11:11:28 +10:00
cris accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
hexagon target/hexagon: Convert to tcg_ops restore_state_to_opc 2022-10-26 11:11:28 +10:00
hppa target/hppa: Move iaoq registers and thus reduce generated code size 2023-08-04 07:33:49 +03:00
i386 target/i386: fix memory operand size for CVTPS2PD 2023-10-04 17:58:16 +03:00
loongarch target/loongarch: Fix the CSRRD CPUID instruction on big endian hosts 2023-07-31 09:12:06 +03:00
m68k target/m68k: Fix semihost lseek offset computation 2023-08-03 08:26:26 +03:00
microblaze accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
mips target/mips: Fix TX79 LQ/SQ opcodes 2023-11-19 21:15:23 +03:00
nios2 target/nios2: Fix semihost lseek offset computation 2023-08-03 08:26:26 +03:00
openrisc accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
ppc target/ppc: Flush inputs to zero with NJ in ppc_store_vscr 2023-09-11 10:53:50 +03:00
riscv target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes 2023-09-13 12:21:22 +03:00
rx Revert incorrect cflags initialization. 2022-10-26 10:53:41 -04:00
s390x target/s390x: Fix LAALG not updating cc_src 2023-11-19 21:15:23 +03:00
sh4 target/sh4: Mask restore of env->flags from tb->flags 2023-03-29 10:20:04 +03:00
sparc target/sparc: Convert to tcg_ops restore_state_to_opc 2022-10-26 11:11:28 +10:00
tricore target/tricore: Rename tricore_feature 2023-11-19 21:15:23 +03:00
xtensa accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00