Max Filippov 10df8ff146 target/xtensa: add MX interrupt controller ... MX interrupt controller is a collection of the following devices accessible through the external registers interface: - interrupt distributor can route each external IRQ line to the corresponding external IRQ pin of selected subset of connected xtensa cores. It has per-CPU and per-IRQ enable signals and per-IRQ software assert signals; - IPI controller has 16 per-CPU IPI signals that may be routed to a combination of 3 designated external IRQ pins of connected xtensa cores; - cache coherecy register controls core L1 cache participation in the SMP cluster cache coherency protocol; - runstall register lets BSP core stall and unstall AP cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2019-01-28 11:55:20 -08:00
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bootparam.h	Clean up ill-advised or unusual header guards	2016-07-12 16:20:46 +02:00
Makefile.objs	target/xtensa: add MX interrupt controller	2019-01-28 11:55:20 -08:00
mx_pic.c	target/xtensa: add MX interrupt controller	2019-01-28 11:55:20 -08:00
pic_cpu.c	target/xtensa: expose core runstall as an IRQ line	2019-01-28 11:55:20 -08:00
sim.c	Change references to serial_hds[] to serial_hd()	2018-04-26 13:57:00 +01:00
xtensa_memory.c	hw/xtensa: extract xtensa_create_memory_regions	2018-01-11 09:31:26 -08:00
xtensa_memory.h	Clean up includes	2018-02-09 05:05:11 +01:00
xtfpga.c	target/xtensa: rearrange access to external interrupts	2019-01-28 11:54:54 -08:00