qemu/target
Daniel Henrique Barboza 1f26c75191 PPC64/TCG: Implement 'rfebb' instruction
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.

The following operations happens during an EBB:

- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).

The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].

This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.

[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:19 +01:00
..
alpha target/alpha: Implement alpha_cpu_record_sigbus 2021-11-02 07:00:52 -04:00
arm Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" 2021-11-22 13:41:48 +00:00
avr target/avr: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
cris target/cris: Make cris_cpu_tlb_fill sysemu only 2021-11-02 07:00:52 -04:00
hexagon This series adds support for the Hexagon Vector eXtensions (HVX) 2021-11-04 06:34:36 -04:00
hppa target/hppa: Make hppa_cpu_tlb_fill sysemu only 2021-11-02 07:00:52 -04:00
i386 Bugfixes for 6.2. 2021-11-19 17:16:57 +01:00
m68k target/m68k: Make m68k_cpu_tlb_fill sysemu only 2021-11-02 07:00:52 -04:00
microblaze target/microblaze: Do not set MO_ALIGN for user-only 2021-11-02 07:00:52 -04:00
mips MIPS patches queue 2021-11-02 15:12:11 -04:00
nios2 target/nios2: Implement nios2_cpu_record_sigsegv 2021-11-02 07:00:52 -04:00
openrisc target/openrisc: Make openrisc_cpu_tlb_fill sysemu only 2021-11-02 07:00:52 -04:00
ppc PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
riscv target/riscv: machine: Sort the .subsections 2021-11-17 19:18:22 +10:00
rx target/rx: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
s390x target/s390x/cpu.h: Remove unused SIGP_MODE defines 2021-11-17 10:17:28 +01:00
sh4 target/sh4: Set fault address in superh_cpu_do_unaligned_access 2021-11-02 07:00:52 -04:00
sparc target/sparc: Set fault address in sparc_cpu_do_unaligned_access 2021-11-02 07:00:52 -04:00
tricore target/tricore: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
xtensa Trivial patches branch pull request 20211101 v2 2021-11-03 11:24:09 -04:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00