a5f56954c7
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-13-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
57 lines
1.8 KiB
C++
57 lines
1.8 KiB
C++
/*
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* Power ISA decode for Vector Facility instructions
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*
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* Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_ALTIVEC(CTX) \
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do { \
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if (unlikely(!(CTX)->altivec_enabled)) { \
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gen_exception((CTX), POWERPC_EXCP_VPU); \
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return true; \
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} \
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} while (0)
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static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
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{
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TCGv_i64 tgt, src, mask;
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_ALTIVEC(ctx);
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tgt = tcg_temp_new_i64();
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src = tcg_temp_new_i64();
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mask = tcg_temp_new_i64();
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/* centrifuge lower double word */
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get_cpu_vsrl(src, a->vra + 32);
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get_cpu_vsrl(mask, a->vrb + 32);
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gen_helper_cfuged(tgt, src, mask);
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set_cpu_vsrl(a->vrt + 32, tgt);
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/* centrifuge higher double word */
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get_cpu_vsrh(src, a->vra + 32);
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get_cpu_vsrh(mask, a->vrb + 32);
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gen_helper_cfuged(tgt, src, mask);
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set_cpu_vsrh(a->vrt + 32, tgt);
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tcg_temp_free_i64(tgt);
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tcg_temp_free_i64(src);
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tcg_temp_free_i64(mask);
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return true;
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}
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