qemu/hw/riscv
Alistair Francis 0feb4a7129
riscv: plic: Fix incorrect irq calculation
This patch fixes four different things, to maintain bisectability they
have been merged into a single patch. The following fixes are below:

sifive_plic: Fix incorrect irq calculation
The irq is incorrectly calculated to be off by one. It has worked in the
past as the priority_base offset has also been set incorrectly. We are
about to fix the priority_base offset so first first the irq
calculation.

sifive_u: Fix PLIC priority base offset and numbering
According to the FU540 manual the PLIC source priority address starts at
an offset of 0x04 and not 0x00. The same manual also specifies that the
PLIC only has 53 source priorities. Fix these two incorrect header
files.

We also need to over extend the plic_gpios[] array as the PLIC sources
count from 1 and not 0.

riscv: sifive_e: Fix PLIC priority base offset
According to the FE31 manual the PLIC source priority address starts at
an offset of 0x04 and not 0x00.

riscv: virt: Fix PLIC priority base offset
Update the virt offsets based on the newly updated SiFive U and SiFive E
offsets.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-04-04 16:36:19 -07:00
..
Kconfig kconfig: add CONFIG_MSI_NONBROKEN 2019-03-18 09:39:57 +01:00
Makefile.objs hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards 2019-02-05 16:50:20 +01:00
riscv_hart.c riscv_hart: Fix crash when introspecting the device 2018-07-19 09:05:48 -07:00
riscv_htif.c hw: Do not include "exec/address-spaces.h" if it is not necessary 2018-06-01 14:15:10 +02:00
sifive_clint.c RISC-V: Fix CLINT timecmp low 32-bit writes 2018-12-20 12:08:43 -08:00
sifive_e.c riscv: Ensure the kernel start address is correctly cast 2019-02-11 15:56:22 -08:00
sifive_plic.c riscv: plic: Fix incorrect irq calculation 2019-04-04 16:36:19 -07:00
sifive_prci.c SiFive RISC-V PRCI Block 2018-03-07 08:30:28 +13:00
sifive_test.c
sifive_u.c riscv: sifive_u: Correct UART0's IRQ in the device tree 2019-03-19 05:18:42 -07:00
sifive_uart.c riscv: sifive_uart: Generate TX interrupt 2019-03-19 05:18:28 -07:00
spike.c riscv: Ensure the kernel start address is correctly cast 2019-02-11 15:56:22 -08:00
virt.c riscv: Ensure the kernel start address is correctly cast 2019-02-11 15:56:22 -08:00