Cédric Le Goater f16c845ade ftgmac100: implement the new MDIO interface on Aspeed SoC ... The PHY behind the MAC of an Aspeed SoC can be controlled using two different MDC/MDIO interfaces. The same registers PHYCR (MAC60) and PHYDATA (MAC64) are involved but they have a different layout. BIT31 of the Feature Register (MAC40) controls which MDC/MDIO interface is active. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190111125759.31577-1-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2019-01-21 10:23:11 +00:00
..
can
fsl_etsec
rocker
allwinner_emac.c
cadence_gem.c
dp8393x.c
e1000_regs.h
e1000.c
e1000e_core.c
e1000e_core.h
e1000e.c
e1000x_common.c
e1000x_common.h
eepro100.c
etraxfs_eth.c
ftgmac100.c
imx_fec.c
lan9118.c
lance.c
Makefile.objs
mcf_fec.c
milkymist-minimac2.c
mipsnet.c
ne2000-isa.c
ne2000.c
ne2000.h
net_rx_pkt.c
net_rx_pkt.h
net_tx_pkt.c
net_tx_pkt.h
opencores_eth.c
pcnet-pci.c
pcnet.c
pcnet.h
rtl8139.c
smc91c111.c
spapr_llan.c
stellaris_enet.c
sungem.c
sunhme.c
trace-events
vhost_net.c
virtio-net.c
vmware_utils.h
vmxnet3_defs.h
vmxnet3.c
vmxnet3.h
vmxnet_debug.h
xen_nic.c
xgmac.c
xilinx_axienet.c
xilinx_ethlite.c