3ee01413be
Failed memory transactions should raise exceptions 14 (for fetch) or 15 (for load/store) with XEA2. Memory accesses that result in TLB miss followed by an attempt to load PTE from physical memory which fails should raise InstTLBMiss or LoadStoreTLBMiss with XEA2. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
125 lines
2.1 KiB
ArmAsm
125 lines
2.1 KiB
ArmAsm
#include "macros.inc"
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test_suite phys_mem
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.purgem test_init
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.macro test_init
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movi a2, 0xc0000003 /* PPN */
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movi a3, 0xc0000004 /* VPN */
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wdtlb a2, a3
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witlb a2, a3
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movi a2, 0xc0000000
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wsr a2, ptevaddr
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.endm
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test inst_fetch_get_pte_no_phys
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set_vector kernel, 2f
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movi a2, 0x20000000
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jx a2
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2:
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movi a2, 0x20000000
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rsr a3, excvaddr
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assert eq, a2, a3
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rsr a3, epc1
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assert eq, a2, a3
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rsr a3, exccause
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movi a2, 16
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assert eq, a2, a3
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test_end
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test read_get_pte_no_phys
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set_vector kernel, 2f
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movi a2, 0x20000000
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1:
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l32i a3, a2, 0
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test_fail
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2:
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movi a2, 0x20000000
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rsr a3, excvaddr
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assert eq, a2, a3
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movi a2, 1b
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rsr a3, epc1
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assert eq, a2, a3
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rsr a3, exccause
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movi a2, 24
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assert eq, a2, a3
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test_end
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test write_get_pte_no_phys
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set_vector kernel, 2f
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movi a2, 0x20000000
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1:
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s32i a3, a2, 0
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test_fail
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2:
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movi a2, 0x20000000
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rsr a3, excvaddr
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assert eq, a2, a3
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movi a2, 1b
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rsr a3, epc1
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assert eq, a2, a3
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rsr a3, exccause
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movi a2, 24
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assert eq, a2, a3
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test_end
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test inst_fetch_no_phys
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set_vector kernel, 2f
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movi a2, 0xc0000000
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jx a2
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2:
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movi a2, 0xc0000000
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rsr a3, excvaddr
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assert eq, a2, a3
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rsr a3, epc1
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assert eq, a2, a3
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rsr a3, exccause
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movi a2, 14
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assert eq, a2, a3
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test_end
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test read_no_phys
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set_vector kernel, 2f
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movi a2, 0xc0000000
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1:
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l32i a3, a2, 0
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test_fail
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2:
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movi a2, 0xc0000000
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rsr a3, excvaddr
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assert eq, a2, a3
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movi a2, 1b
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rsr a3, epc1
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assert eq, a2, a3
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rsr a3, exccause
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movi a2, 15
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assert eq, a2, a3
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test_end
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test write_no_phys
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set_vector kernel, 2f
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movi a2, 0xc0000000
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1:
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s32i a3, a2, 0
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test_fail
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2:
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movi a2, 0xc0000000
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rsr a3, excvaddr
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assert eq, a2, a3
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movi a2, 1b
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rsr a3, epc1
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assert eq, a2, a3
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rsr a3, exccause
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movi a2, 15
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assert eq, a2, a3
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test_end
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test_suite_end
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