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Stephen Long 0ea3ff02c2 target/arm: Implement SVE2 RADDHNB, RADDHNT 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-40-richard.henderson@linaro.org
Message-Id: <20200417162231.10374-3-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25 16:01:44 +01:00
..
a32-uncond.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
a32.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
arch_dump.c
target/arm: add spaces around operator
2020-11-10 11:03:47 +00:00
arm_ldst.h
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
arm-powerctl.c
…
arm-powerctl.h
…
cpu64.c
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
2021-05-25 16:01:43 +01:00
cpu_tcg.c
Revert "target/arm: Make number of counters in PMCR follow the CPU"
2021-04-06 11:49:14 +01:00
cpu-param.h
linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE
2021-02-16 13:06:16 +00:00
cpu-qom.h
qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros
2020-09-18 14:12:32 -04:00
cpu.c
Do not include sysemu/sysemu.h if it's not really necessary
2021-05-02 17:24:50 +02:00
cpu.h
target/arm: Implement SVE2 bitwise permute
2021-05-25 16:01:43 +01:00
crypto_helper.c
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
debug_helper.c
…
gdbstub64.c
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
gdbstub.c
target/arm: use official org.gnu.gdb.aarch64.sve layout for registers
2021-01-18 10:05:06 +00:00
helper-a64.c
target/arm: Add wrapper macros for accessing tbflags
2021-04-30 11:16:50 +01:00
helper-a64.h
target/arm: Merge mte_check1, mte_checkN
2021-04-30 11:16:49 +01:00
helper-sve.h
target/arm: Implement SVE2 RADDHNB, RADDHNT
2021-05-25 16:01:44 +01:00
helper.c
target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
2021-05-25 16:01:43 +01:00
helper.h
target/arm: Implement SVE2 saturating multiply-add high
2021-05-25 16:01:44 +01:00
idau.h
Use DECLARE_*CHECKER* macros
2020-09-09 09:27:09 -04:00
internals.h
target/arm: Rename mte_probe1 to mte_probe
2021-04-30 11:16:49 +01:00
iwmmxt_helper.c
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
kvm64.c
target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
2021-05-25 16:01:43 +01:00
kvm_arm.h
hw/arm/virt: KVM: The IPA lower bound is 32
2021-03-12 12:47:11 +00:00
kvm-consts.h
target/arm: Remove no-longer-reachable 32-bit KVM code
2020-09-14 14:23:19 +01:00
kvm-stub.c
…
kvm.c
hw/arm/virt: KVM: The IPA lower bound is 32
2021-03-12 12:47:11 +00:00
m_helper.c
target/arm: Use correct SP in M-profile exception return
2021-05-25 16:01:43 +01:00
m-nocp.decode
target/arm: Implement new v8.1M VLLDM and VLSTM encodings
2020-12-10 11:44:56 +00:00
machine.c
target/arm: Don't migrate CPUARMState.features
2021-02-11 11:50:13 +00:00
meson.build
target/arm: Make translate-neon.c.inc its own compilation unit
2021-05-10 13:24:09 +01:00
monitor.c
target/arm: Add cpu properties to control pauth
2021-01-19 14:38:51 +00:00
mte_helper.c
target/arm: Rename mte_probe1 to mte_probe
2021-04-30 11:16:49 +01:00
neon_helper.c
target/arm: Split out saturating/rounding shifts from neon
2021-05-25 16:01:43 +01:00
neon-dp.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
neon-ls.decode
target/arm: Fix decode of align in VLDST_single
2021-04-30 11:16:49 +01:00
neon-shared.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
op_addsub.h
…
op_helper.c
target/arm: Make WFI a NOP for userspace emulators
2021-05-10 13:24:09 +01:00
pauth_helper.c
target/arm: Implement an IMPDEF pauth algorithm
2021-01-19 14:38:51 +00:00
psci.c
…
sve_helper.c
target/arm: Implement SVE2 RADDHNB, RADDHNT
2021-05-25 16:01:44 +01:00
sve.decode
target/arm: Implement SVE2 RADDHNB, RADDHNT
2021-05-25 16:01:44 +01:00
syndrome.h
target/arm: Split out syndrome.h from internals.h
2021-02-16 13:16:18 +00:00
t16.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
t32.decode
target/arm: Implement M-profile "minimal RAS implementation"
2020-12-10 11:44:56 +00:00
tlb_helper.c
target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill
2021-03-23 14:07:55 +00:00
trace-events
…
trace.h
trace: switch position of headers to what Meson requires
2020-08-21 06:18:24 -04:00
translate-a32.h
target/arm: Make translate-neon.c.inc its own compilation unit
2021-05-10 13:24:09 +01:00
translate-a64.c
target/arm: Share unallocated_encoding() and gen_exception_insn()
2021-05-10 13:24:09 +01:00
translate-a64.h
target/arm: Share unallocated_encoding() and gen_exception_insn()
2021-05-10 13:24:09 +01:00
translate-m-nocp.c
target/arm: Split m-nocp trans functions into their own file
2021-05-10 13:24:09 +01:00
translate-neon.c
target/arm: Make translate-neon.c.inc its own compilation unit
2021-05-10 13:24:09 +01:00
translate-sve.c
target/arm: Implement SVE2 RADDHNB, RADDHNT
2021-05-25 16:01:44 +01:00
translate-vfp.c
target/arm: Make translate-vfp.c.inc its own compilation unit
2021-05-10 13:24:09 +01:00
translate.c
target/arm: Make sure that commpage's tb->size != 0
2021-05-20 14:19:30 +02:00
translate.h
target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h
2021-05-10 13:24:09 +01:00
vec_helper.c
target/arm: Implement SVE2 complex integer multiply-add
2021-05-25 16:01:44 +01:00
vec_internal.h
target/arm: Implement SVE2 complex integer multiply-add
2021-05-25 16:01:44 +01:00
vfp_helper.c
target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
2020-10-20 16:12:01 +01:00
vfp-uncond.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
vfp.decode
target/arm: Implement VLDR/VSTR system register
2020-12-10 11:44:55 +00:00