d028d02d0c
This driver emulates the ARM AACI interface (PL041) connected to a LM4549 codec. It enables audio playback for the Versatile/PB platform. Limitations: - Supports only a playback on one channel (Versatile/Vexpress) - Supports only one TX FIFO in compact-mode or non-compact mode. - Supports playback of 12, 16, 18 and 20 bits samples. - Record is not supported. - The PL041 is hardwired to a LM4549 codec. Versatile/PB test build: linux-2.6.38.5 buildroot-2010.11 alsa-lib-1.0.22 alsa-utils-1.0.22 mpg123-0.66 Qemu host: Ubuntu 10.04 in Vmware/OS X Playback tested successfully with speaker-test/aplay/mpg123. Signed-off-by: Mathieu Sonet <contact@elasticsheep.com> [Peter Maydell: fixed typo in code clearing SL1RXBUSY/SL2RXBUSY bits, as spotted by Andrzej Zaborowski] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
136 lines
3.4 KiB
C
136 lines
3.4 KiB
C
/*
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* Arm PrimeCell PL041 Advanced Audio Codec Interface
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*
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* Copyright (c) 2011
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* Written by Mathieu Sonet - www.elasticsheep.com
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*
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* This code is licenced under the GPL.
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*
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* *****************************************************************
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*/
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#ifndef HW_PL041_H
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#define HW_PL041_H
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/* Register file */
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#define REGISTER(name, offset) uint32_t name;
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typedef struct {
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#include "pl041.hx"
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} pl041_regfile;
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#undef REGISTER
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/* Register addresses */
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#define REGISTER(name, offset) PL041_##name = offset,
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enum {
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#include "pl041.hx"
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PL041_periphid0 = 0xFE0,
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PL041_periphid1 = 0xFE4,
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PL041_periphid2 = 0xFE8,
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PL041_periphid3 = 0xFEC,
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PL041_pcellid0 = 0xFF0,
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PL041_pcellid1 = 0xFF4,
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PL041_pcellid2 = 0xFF8,
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PL041_pcellid3 = 0xFFC,
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};
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#undef REGISTER
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/* Register bits */
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/* IEx */
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#define TXCIE (1 << 0)
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#define RXTIE (1 << 1)
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#define TXIE (1 << 2)
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#define RXIE (1 << 3)
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#define RXOIE (1 << 4)
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#define TXUIE (1 << 5)
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#define RXTOIE (1 << 6)
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/* TXCRx */
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#define TXEN (1 << 0)
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#define TXSLOT1 (1 << 1)
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#define TXSLOT2 (1 << 2)
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#define TXSLOT3 (1 << 3)
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#define TXSLOT4 (1 << 4)
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#define TXCOMPACT (1 << 15)
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#define TXFEN (1 << 16)
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#define TXSLOT_MASK_BIT (1)
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#define TXSLOT_MASK (0xFFF << TXSLOT_MASK_BIT)
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#define TSIZE_MASK_BIT (13)
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#define TSIZE_MASK (0x3 << TSIZE_MASK_BIT)
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#define TSIZE_16BITS (0x0 << TSIZE_MASK_BIT)
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#define TSIZE_18BITS (0x1 << TSIZE_MASK_BIT)
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#define TSIZE_20BITS (0x2 << TSIZE_MASK_BIT)
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#define TSIZE_12BITS (0x3 << TSIZE_MASK_BIT)
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/* SRx */
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#define RXFE (1 << 0)
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#define TXFE (1 << 1)
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#define RXHF (1 << 2)
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#define TXHE (1 << 3)
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#define RXFF (1 << 4)
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#define TXFF (1 << 5)
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#define RXBUSY (1 << 6)
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#define TXBUSY (1 << 7)
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#define RXOVERRUN (1 << 8)
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#define TXUNDERRUN (1 << 9)
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#define RXTIMEOUT (1 << 10)
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#define RXTOFE (1 << 11)
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/* ISRx */
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#define TXCINTR (1 << 0)
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#define RXTOINTR (1 << 1)
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#define TXINTR (1 << 2)
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#define RXINTR (1 << 3)
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#define ORINTR (1 << 4)
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#define URINTR (1 << 5)
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#define RXTOFEINTR (1 << 6)
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/* SLFR */
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#define SL1RXBUSY (1 << 0)
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#define SL1TXBUSY (1 << 1)
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#define SL2RXBUSY (1 << 2)
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#define SL2TXBUSY (1 << 3)
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#define SL12RXBUSY (1 << 4)
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#define SL12TXBUSY (1 << 5)
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#define SL1RXVALID (1 << 6)
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#define SL1TXEMPTY (1 << 7)
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#define SL2RXVALID (1 << 8)
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#define SL2TXEMPTY (1 << 9)
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#define SL12RXVALID (1 << 10)
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#define SL12TXEMPTY (1 << 11)
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#define RAWGPIOINT (1 << 12)
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#define RWIS (1 << 13)
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/* MAINCR */
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#define AACIFE (1 << 0)
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#define LOOPBACK (1 << 1)
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#define LOWPOWER (1 << 2)
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#define SL1RXEN (1 << 3)
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#define SL1TXEN (1 << 4)
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#define SL2RXEN (1 << 5)
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#define SL2TXEN (1 << 6)
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#define SL12RXEN (1 << 7)
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#define SL12TXEN (1 << 8)
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#define DMAENABLE (1 << 9)
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/* INTCLR */
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#define WISC (1 << 0)
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#define RXOEC1 (1 << 1)
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#define RXOEC2 (1 << 2)
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#define RXOEC3 (1 << 3)
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#define RXOEC4 (1 << 4)
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#define TXUEC1 (1 << 5)
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#define TXUEC2 (1 << 6)
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#define TXUEC3 (1 << 7)
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#define TXUEC4 (1 << 8)
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#define RXTOFEC1 (1 << 9)
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#define RXTOFEC2 (1 << 10)
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#define RXTOFEC3 (1 << 11)
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#define RXTOFEC4 (1 << 12)
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#endif /* #ifndef HW_PL041_H */
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