Bin Meng 0d95299468 riscv: sifive: Implement PRCI model for FU540 ... This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-09-17 08:42:47 -07:00
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boot.h	riscv: Add a helper routine for finding firmware	2019-09-17 08:42:43 -07:00
riscv_hart.h	riscv: hart: Add a "hartid-base" property to RISC-V hart array	2019-09-17 08:42:47 -07:00
riscv_htif.h	Clean up inclusion of sysemu/sysemu.h	2019-08-16 13:31:53 +02:00
sifive_clint.h	include: Make headers more self-contained	2019-08-16 13:31:51 +02:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e_prci.h	riscv: sifive_e: prci: Update the PRCI register block size	2019-09-17 08:42:46 -07:00
sifive_e.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_gpio.h	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
sifive_plic.h	riscv: plic: Remove unused interrupt functions	2019-09-17 08:42:42 -07:00
sifive_test.h	riscv: sifive_test: Add reset functionality	2019-09-17 08:42:44 -07:00
sifive_u_prci.h	riscv: sifive: Implement PRCI model for FU540	2019-09-17 08:42:47 -07:00
sifive_u.h	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	2019-09-17 08:42:47 -07:00
sifive_uart.h	include: Make headers more self-contained	2019-08-16 13:31:51 +02:00
spike.h	include: Make headers more self-contained	2019-08-16 13:31:51 +02:00
virt.h	include: Make headers more self-contained	2019-08-16 13:31:51 +02:00