qemu/target at 0c46a69a5eb8a061134719a0a85898854eb8e533 - qemu

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Peter Maydell e609fa71e8 Tag edgar/xilinx-next-2018-05-29-v1.for-upstream

-----BEGIN PGP SIGNATURE-----
 
 iQEcBAABCAAGBQJbDRY2AAoJECnFlngPa8qDhSgH/jVtKCwHfLfMkFFy4++OP4S3
 9VtJYNm5PX4QJrpRvpuDIzYU6B3WuYvwTyoNg4lbUy7IBR8zqa6b1+fz66S64N8o
 DgkTH6cLlirY52aJbVxLiSqOsCgAx8kWhcWIetraw1Q9tS2ur8pWqcsyawwPhFEo
 +Ck8rl8IvSlzxYWCKshipKliKOjLjrUlIcUlN7OrW+FN8qVCxhcGSVRGDEQVcFvF
 DtM/KI68x97rK8KSRSqHSC926/AV90cUxsz4KQcieL6Aj8bA4RDC0BtSTaV2GxrY
 DmaB9rsvlnb8y9awB6X7gcN4QrPpbp5h07B6eWxZRM2p83Tkg06oUZS1hrNW4zk=
 =uquA
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream' into staging

Tag edgar/xilinx-next-2018-05-29-v1.for-upstream

# gpg: Signature made Tue 29 May 2018 09:58:30 BST
# gpg:                using RSA key 29C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>"
# gpg:                 aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>"
# Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF  4151 29C5 9678 0F6B CA83

* remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream: (38 commits)
  target-microblaze: Consolidate MMU enabled checks
  target-microblaze: cpu_mmu_index: Fixup indentation
  target-microblaze: Use tcg_gen_movcond in eval_cond_jmp
  target-microblaze: Convert env_btarget to i64
  target-microblaze: Remove argument b in eval_cc()
  target-microblaze: Use table based condition-codes conversion
  target-microblaze: mmu: Cleanup debug log messages
  target-microblaze: Simplify address computation using tcg_gen_addi_i32()
  target-microblaze: Allow address sizes between 32 and 64 bits
  target-microblaze: Add support for extended access to TLBLO
  target-microblaze: dec_msr: Plug a temp leak
  target-microblaze: mmu: Add a configurable output address mask
  target-microblaze: mmu: Prepare for 64-bit addresses
  target-microblaze: mmu: Remove unused register state
  target-microblaze: mmu: Add R_TBLX_MISS macros
  target-microblaze: Implement MFSE EAR
  target-microblaze: Add Extended Addressing
  target-microblaze: Setup for 64bit addressing
  target-microblaze: Make special registers 64-bit
  target-microblaze: dec_msr: Fix MTS to FSR
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2018-05-29 13:01:11 +01:00

alpha

target/alpha: Honor CPU_DUMP_FPU

2018-05-18 14:52:38 -07:00

arm

target/arm: Implement SVE Permute - Extract Group

2018-05-18 17:48:09 +01:00

cris

…

hppa

fpu/softfloat: Specialize on snan_bit_is_one

2018-05-17 15:27:15 -07:00