e2392d4395
The BMC of the OpenPOWER systems monitors the machine state using sensors, controls the power and controls the access to the PNOR flash device containing the firmware image required to boot the host. QEMU models the power cycle process, access to the sensors and access to the PNOR device. But, for these features to be available, the QEMU PowerNV machine needs two extras devices on the command line, an IPMI BT device for communication and a BMC backend device: -device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10 The BMC properties are then defined accordingly in the device tree and OPAL self adapts. If a BMC device and an IPMI BT device are not available, OPAL does not try to communicate with the BMC in any manner. This is not how real systems behave. To be closer to the default behavior, create an IPMI BMC simulator device and an IPMI BT device at machine initialization time. We loose the ability to define an external BMC device but there are benefits: - a better match with real systems, - a better test coverage of the OPAL code, - system powerdown and reset commands that work, - a QEMU device tree compliant with the specifications (*). (*) Still needs a MBOX device. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191121162340.11049-1-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
233 lines
6.8 KiB
C
233 lines
6.8 KiB
C
/*
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* QEMU PowerNV, BMC related functions
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*
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* Copyright (c) 2016-2017, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qapi/error.h"
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#include "target/ppc/cpu.h"
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#include "qemu/log.h"
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#include "hw/ipmi/ipmi.h"
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#include "hw/ppc/fdt.h"
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#include "hw/ppc/pnv.h"
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#include <libfdt.h>
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/* TODO: include definition in ipmi.h */
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#define IPMI_SDR_FULL_TYPE 1
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/*
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* OEM SEL Event data packet sent by BMC in response of a Read Event
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* Message Buffer command
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*/
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typedef struct OemSel {
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/* SEL header */
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uint8_t id[2];
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uint8_t type;
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uint8_t timestamp[4];
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uint8_t manuf_id[3];
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/* OEM SEL data (6 bytes) follows */
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uint8_t netfun;
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uint8_t cmd;
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uint8_t data[4];
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} OemSel;
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#define SOFT_OFF 0x00
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#define SOFT_REBOOT 0x01
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static void pnv_gen_oem_sel(IPMIBmc *bmc, uint8_t reboot)
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{
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/* IPMI SEL Event are 16 bytes long */
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OemSel sel = {
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.id = { 0x55 , 0x55 },
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.type = 0xC0, /* OEM */
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.manuf_id = { 0x0, 0x0, 0x0 },
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.timestamp = { 0x0, 0x0, 0x0, 0x0 },
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.netfun = 0x3A, /* IBM */
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.cmd = 0x04, /* AMI OEM SEL Power Notification */
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.data = { reboot, 0xFF, 0xFF, 0xFF },
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};
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ipmi_bmc_gen_event(bmc, (uint8_t *) &sel, 0 /* do not log the event */);
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}
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void pnv_bmc_powerdown(IPMIBmc *bmc)
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{
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pnv_gen_oem_sel(bmc, SOFT_OFF);
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}
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void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt)
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{
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int offset;
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int i;
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const struct ipmi_sdr_compact *sdr;
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uint16_t nextrec;
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offset = fdt_add_subnode(fdt, 0, "bmc");
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_FDT(offset);
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_FDT((fdt_setprop_string(fdt, offset, "name", "bmc")));
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offset = fdt_add_subnode(fdt, offset, "sensors");
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_FDT(offset);
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_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1)));
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_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0)));
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for (i = 0; !ipmi_bmc_sdr_find(bmc, i, &sdr, &nextrec); i++) {
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int off;
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char *name;
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if (sdr->header.rec_type != IPMI_SDR_COMPACT_TYPE &&
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sdr->header.rec_type != IPMI_SDR_FULL_TYPE) {
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continue;
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}
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name = g_strdup_printf("sensor@%x", sdr->sensor_owner_number);
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off = fdt_add_subnode(fdt, offset, name);
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_FDT(off);
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g_free(name);
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_FDT((fdt_setprop_cell(fdt, off, "reg", sdr->sensor_owner_number)));
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_FDT((fdt_setprop_string(fdt, off, "name", "sensor")));
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_FDT((fdt_setprop_string(fdt, off, "compatible", "ibm,ipmi-sensor")));
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_FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-reading-type",
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sdr->reading_type)));
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_FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-id",
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sdr->entity_id)));
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_FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-instance",
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sdr->entity_instance)));
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_FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-type",
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sdr->sensor_type)));
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}
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}
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/*
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* HIOMAP protocol handler
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*/
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#define HIOMAP_C_RESET 1
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#define HIOMAP_C_GET_INFO 2
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#define HIOMAP_C_GET_FLASH_INFO 3
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#define HIOMAP_C_CREATE_READ_WINDOW 4
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#define HIOMAP_C_CLOSE_WINDOW 5
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#define HIOMAP_C_CREATE_WRITE_WINDOW 6
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#define HIOMAP_C_MARK_DIRTY 7
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#define HIOMAP_C_FLUSH 8
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#define HIOMAP_C_ACK 9
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#define HIOMAP_C_ERASE 10
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#define HIOMAP_C_DEVICE_NAME 11
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#define HIOMAP_C_LOCK 12
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#define BLOCK_SHIFT 12 /* 4K */
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static uint16_t bytes_to_blocks(uint32_t bytes)
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{
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return bytes >> BLOCK_SHIFT;
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}
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static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len,
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RspBuffer *rsp)
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{
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PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
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PnvPnor *pnor = pnv->pnor;
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uint32_t pnor_size = pnor->size;
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uint32_t pnor_addr = PNOR_SPI_OFFSET;
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bool readonly = false;
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rsp_buffer_push(rsp, cmd[2]);
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rsp_buffer_push(rsp, cmd[3]);
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switch (cmd[2]) {
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case HIOMAP_C_MARK_DIRTY:
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case HIOMAP_C_FLUSH:
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case HIOMAP_C_ERASE:
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case HIOMAP_C_ACK:
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break;
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case HIOMAP_C_GET_INFO:
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rsp_buffer_push(rsp, 2); /* Version 2 */
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rsp_buffer_push(rsp, BLOCK_SHIFT); /* block size */
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rsp_buffer_push(rsp, 0); /* Timeout */
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rsp_buffer_push(rsp, 0); /* Timeout */
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break;
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case HIOMAP_C_GET_FLASH_INFO:
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rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
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rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
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rsp_buffer_push(rsp, 0x01); /* erase size */
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rsp_buffer_push(rsp, 0x00); /* erase size */
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break;
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case HIOMAP_C_CREATE_READ_WINDOW:
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readonly = true;
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/* Fall through */
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case HIOMAP_C_CREATE_WRITE_WINDOW:
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memory_region_set_readonly(&pnor->mmio, readonly);
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memory_region_set_enabled(&pnor->mmio, true);
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rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) & 0xFF);
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rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) >> 8);
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rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF);
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rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8);
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rsp_buffer_push(rsp, 0x00); /* offset */
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rsp_buffer_push(rsp, 0x00); /* offset */
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break;
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case HIOMAP_C_CLOSE_WINDOW:
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memory_region_set_enabled(&pnor->mmio, false);
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break;
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case HIOMAP_C_DEVICE_NAME:
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case HIOMAP_C_RESET:
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case HIOMAP_C_LOCK:
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "HIOMAP: unknow command %02X\n", cmd[2]);
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break;
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}
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}
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#define HIOMAP 0x5a
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static const IPMICmdHandler hiomap_cmds[] = {
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[HIOMAP] = { hiomap_cmd, 3 },
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};
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static const IPMINetfn hiomap_netfn = {
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.cmd_nums = ARRAY_SIZE(hiomap_cmds),
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.cmd_handlers = hiomap_cmds
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};
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/*
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* Instantiate the machine BMC. PowerNV uses the QEMU internal
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* simulator but it could also be external.
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*/
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IPMIBmc *pnv_bmc_create(void)
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{
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Object *obj;
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obj = object_new(TYPE_IPMI_BMC_SIMULATOR);
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object_property_set_bool(obj, true, "realized", &error_fatal);
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/* Install the HIOMAP protocol handlers to access the PNOR */
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ipmi_sim_register_netfn(IPMI_BMC_SIMULATOR(obj), IPMI_NETFN_OEM,
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&hiomap_netfn);
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return IPMI_BMC(obj);
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}
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