Peter Maydell 76302a95e7 target/xtensa updates: ... - add libisa to the xtensa target; - change xtensa instruction translator to use it; - switch existing xtensa cores to use it; - add support for a number of instructions: salt/saltu, const16, GPIO32 group, debug mode and MMU-related; - add disassembler for Xtensa. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJaVQW2AAoJEFH5zJH4P6BEQ4EP/01BnD+SoHkDDRx8O59RgvUa r4kkJIqRNpObzzjhoHmh9RbGstir9r1u3ZYKbdlhPgZWK/ItUVzS8yJp8KcQ8x4B Z+4JzwX82PwAvvVdP7TD6iB23jqgUcoEdCtpaUb1jsK0tyvVHwIHnwF3qINY6Nsn yIzmupdIc47MEFlQNSxF/ZuvQI6CT8uDFuRJlK02dv8lEozUXCi9UHotICnqOybY ezgXCoMrOv7UqBdSEX7SQHvs5CD8zRbfhrwpeMc59YsbWp4j5JmQi1QI2ihFHyDN wp5vBDMI31SRdIqpEJiNEP5J+VnVg2oaJZcFP12JGXfTvSyB2WWSfqvQX+go394r 4NbWu1rA/a0vQVUfI7xVqY9mXqGnRbDS01ILYHbjRl14o7kZY0IpX2UIoGXI2eO9 toC+shIv/yNIJoaTlQf3ER+0nUvNFEGbBq3LNB+dlom8yqv7UY2LgpRy4zGqEfyL bB4pfEkaZVqP8vAJeq0TALMTmpvPjgFs1XxnHJAcpoAF3NM8dHiuGpO3li1jPiVu ZxN/8rWSWdJX7IvXFmu3Cy2ogLpdTxsTPIdtpKc+OLHNW6b5wx28Godig7JlfNil 8p9F1t6ZNvs4fPM2JFWP9VTXhzSuynWYz/UEr1+OF7vxni/x7dgrX2h9Houx36/e 3fn34SXgQUqhgtN+8BFR =PNwZ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20180109-xtensa' into staging target/xtensa updates: - add libisa to the xtensa target; - change xtensa instruction translator to use it; - switch existing xtensa cores to use it; - add support for a number of instructions: salt/saltu, const16, GPIO32 group, debug mode and MMU-related; - add disassembler for Xtensa. # gpg: Signature made Tue 09 Jan 2018 18:11:02 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180109-xtensa: target/xtensa: implement disassembler target/xtensa: implement const16 target/xtensa: implement GPIO32 target/xtensa: implement salt/saltu target/xtensa: add internal/noop SRs and opcodes target/xtensa: drop DisasContext::litbase target/xtensa: tests: fix memctl SR test target/xtensa: use libisa for instruction decoding target/xtensa: switch fsf to libisa target/xtensa: switch dc233c to libisa target/xtensa: switch dc232b to libisa target/xtensa: update import_core.sh script for libisa target/xtensa: extract FPU2000 opcode translators target/xtensa: extract core opcode translators target/xtensa: import libisa source target/xtensa: pass actual frame size to the entry helper Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2018-01-09 18:23:27 +00:00
..
libvixl
alpha.c
arm-a64.cc
arm.c	disas/arm: fix 'instuction' typo in comment	2017-12-18 17:07:02 +03:00
cris.c
hppa.c
i386.c	disas/i386: Add disassembly of rorx	2017-09-06 07:19:00 -07:00
lm32.c
m68k.c
Makefile.objs	target/xtensa: implement disassembler	2018-01-09 09:55:39 -08:00
microblaze.c
mips.c
moxie.c
nios2.c	nios2: remove duplicated includes (in code commented out)	2017-12-18 17:07:02 +03:00
ppc.c
s390.c
sh4.c
sparc.c
tci.c
xtensa.c	target/xtensa: implement disassembler	2018-01-09 09:55:39 -08:00