526dbbe087
The NPCM7xx chips have multiple GPIO controllers that are mostly identical except for some minor differences like the reset values of some registers. Each controller controls up to 32 pins. Each individual pin is modeled as a pair of unnamed GPIOs -- one for emitting the actual pin state, and one for driving the pin externally. Like the nRF51 GPIO controller, a gpio level may be negative, which means the pin is not driven, or floating. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
93 lines
2.9 KiB
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93 lines
2.9 KiB
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Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
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=====================================================
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The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
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designed to be used as Baseboard Management Controllers (BMCs) in various
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servers. They all feature one or two ARM Cortex A9 CPU cores, as well as an
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assortment of peripherals targeted for either Enterprise or Data Center /
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Hyperscale applications. The former is a superset of the latter, so NPCM750 has
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all the peripherals of NPCM730 and more.
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.. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
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The NPCM750 SoC has two Cortex A9 cores and is targeted for the Enterprise
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segment. The following machines are based on this chip :
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- ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
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The NPCM730 SoC has two Cortex A9 cores and is targeted for Data Center and
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Hyperscale applications. The following machines are based on this chip :
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- ``quanta-gsj`` Quanta GSJ server BMC
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There are also two more SoCs, NPCM710 and NPCM705, which are single-core
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variants of NPCM750 and NPCM730, respectively. These are currently not
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supported by QEMU.
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Supported devices
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-----------------
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* SMP (Dual Core Cortex-A9)
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* Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer
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and Watchdog.
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* SRAM, ROM and DRAM mappings
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* System Global Control Registers (GCR)
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* Clock and reset controller (CLK)
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* Timer controller (TIM)
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* Serial ports (16550-based)
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* DDR4 memory controller (dummy interface indicating memory training is done)
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* OTP controllers (no protection features)
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* Flash Interface Unit (FIU; no protection features)
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* Random Number Generator (RNG)
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* USB host (USBH)
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* GPIO controller
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Missing devices
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---------------
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* LPC/eSPI host-to-BMC interface, including
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* Keyboard and mouse controller interface (KBCI)
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* Keyboard Controller Style (KCS) channels
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* BIOS POST code FIFO
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* System Wake-up Control (SWC)
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* Shared memory (SHM)
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* eSPI slave interface
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* Ethernet controllers (GMAC and EMC)
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* USB device (USBD)
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* SMBus controller (SMBF)
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* Peripheral SPI controller (PSPI)
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* Analog to Digital Converter (ADC)
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* SD/MMC host
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* PECI interface
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* Pulse Width Modulation (PWM)
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* Tachometer
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* PCI and PCIe root complex and bridges
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* VDM and MCTP support
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* Serial I/O expansion
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* LPC/eSPI host
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* Coprocessor
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* Graphics
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* Video capture
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* Encoding compression engine
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* Security features
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Boot options
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------------
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The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
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a kernel using the ``-kernel`` option. OpenBMC images for `quanta-gsj` and
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possibly others can be downloaded from the OpenPOWER jenkins :
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https://openpower.xyz/
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The firmware image should be attached as an MTD drive. Example :
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.. code-block:: bash
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$ qemu-system-arm -machine quanta-gsj -nographic \
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-drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw
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The default root password for test images is usually ``0penBmc``.
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