5ee5993001
IRQ modification is part of device emulation and should be done while the BQL is held to prevent races when MTTCG is enabled. This adds assertions in the hw emulation layer and wraps the calls from helpers in the BQL. Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
456 lines
11 KiB
C
456 lines
11 KiB
C
/*
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* Helpers for CWP and PSTATE handling
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "trace.h"
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static inline void memcpy32(target_ulong *dst, const target_ulong *src)
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{
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dst[0] = src[0];
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dst[1] = src[1];
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dst[2] = src[2];
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dst[3] = src[3];
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dst[4] = src[4];
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dst[5] = src[5];
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dst[6] = src[6];
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dst[7] = src[7];
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}
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void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
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{
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/* put the modified wrap registers at their proper location */
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if (env->cwp == env->nwindows - 1) {
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memcpy32(env->regbase, env->regbase + env->nwindows * 16);
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}
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env->cwp = new_cwp;
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/* put the wrap registers at their temporary location */
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if (new_cwp == env->nwindows - 1) {
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memcpy32(env->regbase + env->nwindows * 16, env->regbase);
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}
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env->regwptr = env->regbase + (new_cwp * 16);
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}
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target_ulong cpu_get_psr(CPUSPARCState *env)
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{
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helper_compute_psr(env);
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#if !defined(TARGET_SPARC64)
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return env->version | (env->psr & PSR_ICC) |
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(env->psref ? PSR_EF : 0) |
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(env->psrpil << 8) |
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(env->psrs ? PSR_S : 0) |
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(env->psrps ? PSR_PS : 0) |
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(env->psret ? PSR_ET : 0) | env->cwp;
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#else
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return env->psr & PSR_ICC;
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#endif
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}
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void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val)
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{
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env->psr = val & PSR_ICC;
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#if !defined(TARGET_SPARC64)
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env->psref = (val & PSR_EF) ? 1 : 0;
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env->psrpil = (val & PSR_PIL) >> 8;
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env->psrs = (val & PSR_S) ? 1 : 0;
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env->psrps = (val & PSR_PS) ? 1 : 0;
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env->psret = (val & PSR_ET) ? 1 : 0;
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#endif
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env->cc_op = CC_OP_FLAGS;
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#if !defined(TARGET_SPARC64)
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cpu_set_cwp(env, val & PSR_CWP);
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#endif
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}
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/* Called with BQL held */
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void cpu_put_psr(CPUSPARCState *env, target_ulong val)
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{
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cpu_put_psr_raw(env, val);
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#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
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cpu_check_irqs(env);
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#endif
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}
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int cpu_cwp_inc(CPUSPARCState *env, int cwp)
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{
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if (unlikely(cwp >= env->nwindows)) {
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cwp -= env->nwindows;
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}
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return cwp;
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}
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int cpu_cwp_dec(CPUSPARCState *env, int cwp)
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{
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if (unlikely(cwp < 0)) {
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cwp += env->nwindows;
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}
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return cwp;
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}
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#ifndef TARGET_SPARC64
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void helper_rett(CPUSPARCState *env)
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{
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unsigned int cwp;
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if (env->psret == 1) {
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cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC());
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}
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env->psret = 1;
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cwp = cpu_cwp_inc(env, env->cwp + 1) ;
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if (env->wim & (1 << cwp)) {
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cpu_raise_exception_ra(env, TT_WIN_UNF, GETPC());
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}
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cpu_set_cwp(env, cwp);
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env->psrs = env->psrps;
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}
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/* XXX: use another pointer for %iN registers to avoid slow wrapping
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handling ? */
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void helper_save(CPUSPARCState *env)
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{
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uint32_t cwp;
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cwp = cpu_cwp_dec(env, env->cwp - 1);
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if (env->wim & (1 << cwp)) {
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cpu_raise_exception_ra(env, TT_WIN_OVF, GETPC());
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}
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cpu_set_cwp(env, cwp);
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}
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void helper_restore(CPUSPARCState *env)
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{
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uint32_t cwp;
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cwp = cpu_cwp_inc(env, env->cwp + 1);
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if (env->wim & (1 << cwp)) {
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cpu_raise_exception_ra(env, TT_WIN_UNF, GETPC());
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}
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cpu_set_cwp(env, cwp);
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}
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void helper_wrpsr(CPUSPARCState *env, target_ulong new_psr)
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{
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if ((new_psr & PSR_CWP) >= env->nwindows) {
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cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC());
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} else {
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/* cpu_put_psr may trigger interrupts, hence BQL */
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qemu_mutex_lock_iothread();
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cpu_put_psr(env, new_psr);
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qemu_mutex_unlock_iothread();
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}
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}
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target_ulong helper_rdpsr(CPUSPARCState *env)
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{
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return cpu_get_psr(env);
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}
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#else
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/* XXX: use another pointer for %iN registers to avoid slow wrapping
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handling ? */
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void helper_save(CPUSPARCState *env)
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{
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uint32_t cwp;
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cwp = cpu_cwp_dec(env, env->cwp - 1);
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if (env->cansave == 0) {
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int tt = TT_SPILL | (env->otherwin != 0
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? (TT_WOTHER | ((env->wstate & 0x38) >> 1))
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: ((env->wstate & 0x7) << 2));
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cpu_raise_exception_ra(env, tt, GETPC());
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} else {
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if (env->cleanwin - env->canrestore == 0) {
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/* XXX Clean windows without trap */
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cpu_raise_exception_ra(env, TT_CLRWIN, GETPC());
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} else {
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env->cansave--;
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env->canrestore++;
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cpu_set_cwp(env, cwp);
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}
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}
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}
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void helper_restore(CPUSPARCState *env)
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{
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uint32_t cwp;
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cwp = cpu_cwp_inc(env, env->cwp + 1);
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if (env->canrestore == 0) {
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int tt = TT_FILL | (env->otherwin != 0
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? (TT_WOTHER | ((env->wstate & 0x38) >> 1))
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: ((env->wstate & 0x7) << 2));
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cpu_raise_exception_ra(env, tt, GETPC());
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} else {
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env->cansave++;
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env->canrestore--;
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cpu_set_cwp(env, cwp);
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}
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}
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void helper_flushw(CPUSPARCState *env)
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{
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if (env->cansave != env->nwindows - 2) {
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int tt = TT_SPILL | (env->otherwin != 0
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? (TT_WOTHER | ((env->wstate & 0x38) >> 1))
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: ((env->wstate & 0x7) << 2));
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cpu_raise_exception_ra(env, tt, GETPC());
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}
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}
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void helper_saved(CPUSPARCState *env)
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{
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env->cansave++;
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if (env->otherwin == 0) {
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env->canrestore--;
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} else {
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env->otherwin--;
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}
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}
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void helper_restored(CPUSPARCState *env)
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{
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env->canrestore++;
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if (env->cleanwin < env->nwindows - 1) {
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env->cleanwin++;
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}
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if (env->otherwin == 0) {
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env->cansave--;
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} else {
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env->otherwin--;
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}
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}
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target_ulong cpu_get_ccr(CPUSPARCState *env)
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{
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target_ulong psr;
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psr = cpu_get_psr(env);
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return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
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}
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void cpu_put_ccr(CPUSPARCState *env, target_ulong val)
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{
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env->xcc = (val >> 4) << 20;
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env->psr = (val & 0xf) << 20;
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CC_OP = CC_OP_FLAGS;
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}
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target_ulong cpu_get_cwp64(CPUSPARCState *env)
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{
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return env->nwindows - 1 - env->cwp;
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}
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void cpu_put_cwp64(CPUSPARCState *env, int cwp)
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{
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if (unlikely(cwp >= env->nwindows || cwp < 0)) {
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cwp %= env->nwindows;
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}
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cpu_set_cwp(env, env->nwindows - 1 - cwp);
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}
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target_ulong helper_rdccr(CPUSPARCState *env)
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{
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return cpu_get_ccr(env);
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}
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void helper_wrccr(CPUSPARCState *env, target_ulong new_ccr)
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{
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cpu_put_ccr(env, new_ccr);
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}
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/* CWP handling is reversed in V9, but we still use the V8 register
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order. */
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target_ulong helper_rdcwp(CPUSPARCState *env)
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{
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return cpu_get_cwp64(env);
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}
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void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
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{
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cpu_put_cwp64(env, new_cwp);
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}
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static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
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{
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if (env->def->features & CPU_FEATURE_GL) {
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return env->glregs + (env->gl & 7) * 8;
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}
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switch (pstate) {
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default:
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trace_win_helper_gregset_error(pstate);
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/* pass through to normal set of global registers */
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case 0:
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return env->bgregs;
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case PS_AG:
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return env->agregs;
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case PS_MG:
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return env->mgregs;
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case PS_IG:
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return env->igregs;
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}
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}
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static inline uint64_t *get_gl_gregset(CPUSPARCState *env, uint32_t gl)
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{
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return env->glregs + (gl & 7) * 8;
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}
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/* Switch global register bank */
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void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl)
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{
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uint64_t *src, *dst;
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src = get_gl_gregset(env, new_gl);
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dst = get_gl_gregset(env, env->gl);
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if (src != dst) {
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memcpy32(dst, env->gregs);
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memcpy32(env->gregs, src);
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}
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}
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void helper_wrgl(CPUSPARCState *env, target_ulong new_gl)
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{
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cpu_gl_switch_gregs(env, new_gl & 7);
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env->gl = new_gl & 7;
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}
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void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
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{
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uint32_t pstate_regs, new_pstate_regs;
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uint64_t *src, *dst;
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if (env->def->features & CPU_FEATURE_GL) {
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/* PS_AG, IG and MG are not implemented in this case */
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new_pstate &= ~(PS_AG | PS_IG | PS_MG);
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env->pstate = new_pstate;
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return;
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}
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pstate_regs = env->pstate & 0xc01;
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new_pstate_regs = new_pstate & 0xc01;
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if (new_pstate_regs != pstate_regs) {
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trace_win_helper_switch_pstate(pstate_regs, new_pstate_regs);
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/* Switch global register bank */
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src = get_gregset(env, new_pstate_regs);
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dst = get_gregset(env, pstate_regs);
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memcpy32(dst, env->gregs);
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memcpy32(env->gregs, src);
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} else {
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trace_win_helper_no_switch_pstate(new_pstate_regs);
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}
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env->pstate = new_pstate;
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}
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void helper_wrpstate(CPUSPARCState *env, target_ulong new_state)
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{
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cpu_change_pstate(env, new_state & 0xf3f);
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#if !defined(CONFIG_USER_ONLY)
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if (cpu_interrupts_enabled(env)) {
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qemu_mutex_lock_iothread();
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cpu_check_irqs(env);
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qemu_mutex_unlock_iothread();
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}
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#endif
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}
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void helper_wrpil(CPUSPARCState *env, target_ulong new_pil)
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{
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#if !defined(CONFIG_USER_ONLY)
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trace_win_helper_wrpil(env->psrpil, (uint32_t)new_pil);
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env->psrpil = new_pil;
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if (cpu_interrupts_enabled(env)) {
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qemu_mutex_lock_iothread();
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cpu_check_irqs(env);
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qemu_mutex_unlock_iothread();
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}
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#endif
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}
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void helper_done(CPUSPARCState *env)
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{
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trap_state *tsptr = cpu_tsptr(env);
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env->pc = tsptr->tnpc;
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env->npc = tsptr->tnpc + 4;
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cpu_put_ccr(env, tsptr->tstate >> 32);
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env->asi = (tsptr->tstate >> 24) & 0xff;
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cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
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cpu_put_cwp64(env, tsptr->tstate & 0xff);
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if (cpu_has_hypervisor(env)) {
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uint32_t new_gl = (tsptr->tstate >> 40) & 7;
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env->hpstate = env->htstate[env->tl];
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cpu_gl_switch_gregs(env, new_gl);
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env->gl = new_gl;
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}
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env->tl--;
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trace_win_helper_done(env->tl);
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#if !defined(CONFIG_USER_ONLY)
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if (cpu_interrupts_enabled(env)) {
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qemu_mutex_lock_iothread();
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cpu_check_irqs(env);
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qemu_mutex_unlock_iothread();
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}
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#endif
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}
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void helper_retry(CPUSPARCState *env)
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{
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trap_state *tsptr = cpu_tsptr(env);
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env->pc = tsptr->tpc;
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env->npc = tsptr->tnpc;
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cpu_put_ccr(env, tsptr->tstate >> 32);
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env->asi = (tsptr->tstate >> 24) & 0xff;
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cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
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cpu_put_cwp64(env, tsptr->tstate & 0xff);
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if (cpu_has_hypervisor(env)) {
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uint32_t new_gl = (tsptr->tstate >> 40) & 7;
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env->hpstate = env->htstate[env->tl];
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cpu_gl_switch_gregs(env, new_gl);
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env->gl = new_gl;
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}
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env->tl--;
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trace_win_helper_retry(env->tl);
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#if !defined(CONFIG_USER_ONLY)
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if (cpu_interrupts_enabled(env)) {
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qemu_mutex_lock_iothread();
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cpu_check_irqs(env);
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qemu_mutex_unlock_iothread();
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}
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#endif
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}
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#endif
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