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0857a06ef7
qemu/target-xtensa
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Max Filippov 0857a06ef7 target-xtensa: don't generate dead code to access invalid SRs 
This fixes the following test failure caused by access to undefined SR:

    qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting  -kernel ./test_sr.tst
    QEMU 1.4.50 monitor - type 'help' for more information
    (qemu) QEMU 1.4.50 monitor - type 'help' for more information
    (qemu) qemu-system-xtensa: tcg/tcg.c:1673: temp_save: Assertion `s->temps[temp].val_type == 2 || s->temps[temp].fixed_reg' failed.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29 18:35:45 +04:00
..
core-dc232b
core-dc233c
core-fsf
core-dc232b.c misc: move include files to include/qemu/ 2012-12-19 08:32:39 +01:00
core-dc233c.c misc: move include files to include/qemu/ 2012-12-19 08:32:39 +01:00
core-fsf.c misc: move include files to include/qemu/ 2012-12-19 08:32:39 +01:00
cpu-qom.h cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
cpu.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
cpu.h target-xtensa: avoid double-stopping at breakpoints 2013-07-29 18:35:45 +04:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
helper.c cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs 2013-07-26 23:23:54 +02:00
helper.h exec: move include files to include/exec/ 2012-12-19 08:31:31 +01:00
Makefile.objs cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
op_helper.c target-xtensa: avoid double-stopping at breakpoints 2013-07-29 18:35:45 +04:00
overlay_tool.h target-xtensa: implement MISC SR 2012-12-08 18:48:26 +00:00
translate.c target-xtensa: don't generate dead code to access invalid SRs 2013-07-29 18:35:45 +04:00
xtensa-semi.c exec: Change cpu_memory_rw_debug() argument to CPUState 2013-07-23 02:41:33 +02:00