412 lines
12 KiB
C
412 lines
12 KiB
C
/*
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* Helpers for HPPA instructions.
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#include "qemu/timer.h"
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#include "trace.h"
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G_NORETURN void HELPER(excp)(CPUHPPAState *env, int excp)
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{
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CPUState *cs = env_cpu(env);
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cs->exception_index = excp;
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cpu_loop_exit(cs);
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}
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G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra)
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{
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CPUState *cs = env_cpu(env);
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cs->exception_index = excp;
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cpu_loop_exit_restore(cs, ra);
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}
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void HELPER(tsv)(CPUHPPAState *env, target_ulong cond)
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{
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if (unlikely((target_long)cond < 0)) {
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hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC());
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}
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}
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void HELPER(tcond)(CPUHPPAState *env, target_ulong cond)
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{
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if (unlikely(cond)) {
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hppa_dynamic_excp(env, EXCP_COND, GETPC());
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}
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}
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static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr,
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uint32_t val, uint32_t mask, uintptr_t ra)
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{
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int mmu_idx = cpu_mmu_index(env, 0);
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uint32_t old, new, cmp, *haddr;
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void *vaddr;
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vaddr = probe_access(env, addr, 3, MMU_DATA_STORE, mmu_idx, ra);
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if (vaddr == NULL) {
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cpu_loop_exit_atomic(env_cpu(env), ra);
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}
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haddr = (uint32_t *)((uintptr_t)vaddr & -4);
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mask = addr & 1 ? 0x00ffffffu : 0xffffff00u;
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old = *haddr;
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while (1) {
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new = be32_to_cpu((cpu_to_be32(old) & ~mask) | (val & mask));
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cmp = qatomic_cmpxchg(haddr, old, new);
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if (cmp == old) {
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return;
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}
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old = cmp;
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}
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}
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static void atomic_store_mask64(CPUHPPAState *env, target_ulong addr,
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uint64_t val, uint64_t mask,
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int size, uintptr_t ra)
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{
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#ifdef CONFIG_ATOMIC64
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int mmu_idx = cpu_mmu_index(env, 0);
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uint64_t old, new, cmp, *haddr;
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void *vaddr;
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vaddr = probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, ra);
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if (vaddr == NULL) {
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cpu_loop_exit_atomic(env_cpu(env), ra);
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}
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haddr = (uint64_t *)((uintptr_t)vaddr & -8);
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old = *haddr;
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while (1) {
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new = be32_to_cpu((cpu_to_be32(old) & ~mask) | (val & mask));
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cmp = qatomic_cmpxchg__nocheck(haddr, old, new);
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if (cmp == old) {
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return;
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}
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old = cmp;
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}
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#else
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cpu_loop_exit_atomic(env_cpu(env), ra);
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#endif
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}
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static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val,
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bool parallel, uintptr_t ra)
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{
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switch (addr & 3) {
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case 3:
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cpu_stb_data_ra(env, addr, val, ra);
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break;
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case 2:
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cpu_stw_data_ra(env, addr, val, ra);
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break;
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case 1:
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/* The 3 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
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} else {
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cpu_stb_data_ra(env, addr, val >> 16, ra);
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cpu_stw_data_ra(env, addr + 1, val, ra);
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}
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break;
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default:
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cpu_stl_data_ra(env, addr, val, ra);
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break;
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}
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}
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static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
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bool parallel, uintptr_t ra)
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{
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switch (addr & 7) {
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case 7:
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cpu_stb_data_ra(env, addr, val, ra);
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break;
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case 6:
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cpu_stw_data_ra(env, addr, val, ra);
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break;
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case 5:
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/* The 3 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
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} else {
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cpu_stb_data_ra(env, addr, val >> 16, ra);
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cpu_stw_data_ra(env, addr + 1, val, ra);
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}
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break;
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case 4:
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cpu_stl_data_ra(env, addr, val, ra);
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break;
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case 3:
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/* The 5 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask64(env, addr, val, 0x000000ffffffffffull, 5, ra);
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} else {
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cpu_stb_data_ra(env, addr, val >> 32, ra);
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cpu_stl_data_ra(env, addr + 1, val, ra);
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}
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break;
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case 2:
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/* The 6 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask64(env, addr, val, 0x0000ffffffffffffull, 6, ra);
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} else {
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cpu_stw_data_ra(env, addr, val >> 32, ra);
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cpu_stl_data_ra(env, addr + 2, val, ra);
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}
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break;
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case 1:
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/* The 7 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask64(env, addr, val, 0x00ffffffffffffffull, 7, ra);
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} else {
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cpu_stb_data_ra(env, addr, val >> 48, ra);
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cpu_stw_data_ra(env, addr + 1, val >> 32, ra);
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cpu_stl_data_ra(env, addr + 3, val, ra);
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}
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break;
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default:
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cpu_stq_data_ra(env, addr, val, ra);
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break;
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}
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}
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void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val)
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{
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do_stby_b(env, addr, val, false, GETPC());
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}
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void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr,
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target_ulong val)
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{
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do_stby_b(env, addr, val, true, GETPC());
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}
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void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val)
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{
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do_stdby_b(env, addr, val, false, GETPC());
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}
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void HELPER(stdby_b_parallel)(CPUHPPAState *env, target_ulong addr,
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target_ulong val)
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{
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do_stdby_b(env, addr, val, true, GETPC());
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}
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static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val,
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bool parallel, uintptr_t ra)
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{
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switch (addr & 3) {
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case 3:
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/* The 3 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra);
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} else {
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cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
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cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
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}
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break;
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case 2:
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cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
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break;
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case 1:
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cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
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break;
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default:
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/* Nothing is stored, but protection is checked and the
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cacheline is marked dirty. */
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probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra);
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break;
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}
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}
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static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
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bool parallel, uintptr_t ra)
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{
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switch (addr & 7) {
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case 7:
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/* The 7 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask64(env, addr - 7, val,
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0xffffffffffffff00ull, 7, ra);
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} else {
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cpu_stl_data_ra(env, addr - 7, val >> 32, ra);
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cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
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cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
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}
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break;
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case 6:
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/* The 6 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask64(env, addr - 6, val,
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0xffffffffffff0000ull, 6, ra);
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} else {
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cpu_stl_data_ra(env, addr - 6, val >> 32, ra);
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cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
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}
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break;
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case 5:
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/* The 5 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask64(env, addr - 5, val,
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0xffffffffff000000ull, 5, ra);
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} else {
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cpu_stl_data_ra(env, addr - 5, val >> 32, ra);
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cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
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}
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break;
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case 4:
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cpu_stl_data_ra(env, addr - 4, val >> 32, ra);
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break;
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case 3:
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/* The 3 byte store must appear atomic. */
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if (parallel) {
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atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra);
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} else {
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cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
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cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
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}
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break;
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case 2:
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cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
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break;
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case 1:
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cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
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break;
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default:
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/* Nothing is stored, but protection is checked and the
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cacheline is marked dirty. */
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probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra);
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break;
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}
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}
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void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val)
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{
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do_stby_e(env, addr, val, false, GETPC());
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}
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void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr,
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target_ulong val)
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{
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do_stby_e(env, addr, val, true, GETPC());
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}
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void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val)
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{
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do_stdby_e(env, addr, val, false, GETPC());
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}
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void HELPER(stdby_e_parallel)(CPUHPPAState *env, target_ulong addr,
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target_ulong val)
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{
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do_stdby_e(env, addr, val, true, GETPC());
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}
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void HELPER(ldc_check)(target_ulong addr)
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{
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if (unlikely(addr & 0xf)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Undefined ldc to unaligned address mod 16: "
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TARGET_FMT_lx "\n", addr);
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}
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}
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target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr,
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uint32_t level, uint32_t want)
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{
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#ifdef CONFIG_USER_ONLY
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return page_check_range(addr, 1, want);
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#else
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int prot, excp;
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hwaddr phys;
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trace_hppa_tlb_probe(addr, level, want);
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/* Fail if the requested privilege level is higher than current. */
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if (level < (env->iaoq_f & 3)) {
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return 0;
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}
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excp = hppa_get_physical_address(env, addr, level, 0, &phys,
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&prot, NULL);
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if (excp >= 0) {
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if (env->psw & PSW_Q) {
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/* ??? Needs tweaking for hppa64. */
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env->cr[CR_IOR] = addr;
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env->cr[CR_ISR] = addr >> 32;
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}
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if (excp == EXCP_DTLB_MISS) {
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excp = EXCP_NA_DTLB_MISS;
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}
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hppa_dynamic_excp(env, excp, GETPC());
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}
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return (want & prot) != 0;
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#endif
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}
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target_ulong HELPER(read_interval_timer)(void)
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{
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#ifdef CONFIG_USER_ONLY
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/* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist.
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Just pass through the host cpu clock ticks. */
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return cpu_get_host_ticks();
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#else
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/* In system mode we have access to a decent high-resolution clock.
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In order to make OS-level time accounting work with the cr16,
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present it with a well-timed clock fixed at 250MHz. */
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return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2;
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#endif
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}
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uint64_t HELPER(hadd_ss)(uint64_t r1, uint64_t r2)
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{
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uint64_t ret = 0;
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for (int i = 0; i < 64; i += 16) {
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int f1 = sextract64(r1, i, 16);
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int f2 = sextract64(r2, i, 16);
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int fr = f1 + f2;
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fr = MIN(fr, INT16_MAX);
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fr = MAX(fr, INT16_MIN);
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ret = deposit64(ret, i, 16, fr);
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}
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return ret;
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}
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uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2)
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{
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uint64_t ret = 0;
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for (int i = 0; i < 64; i += 16) {
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int f1 = extract64(r1, i, 16);
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int f2 = sextract64(r2, i, 16);
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int fr = f1 + f2;
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fr = MIN(fr, UINT16_MAX);
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fr = MAX(fr, 0);
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ret = deposit64(ret, i, 16, fr);
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}
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return ret;
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}
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