07e2034d08
Add state information to GICv3 object structure and implement arm_gicv3_common_reset(). This commit includes accessor functions for the fields which are stored as bitmaps in uint32_t arrays. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-7-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled: * Add missing qom/cpu.h include * Remove legacy-only state fields (we can add them later if/when we add legacy emulation) * Use arrays of uint32_t to store the various distributor bitmaps, and provide accessor functions for the various set/test/etc operations * Add various missing register offset #defines * Accessor macros which combine distributor and redistributor behaviour removed * Fields in state structures renamed to match architectural register names * Corrected the reset value for GICR_IENABLER0 since we don't support legacy mode * Added ARM_LINUX_BOOT_IF interface for "we are directly booting a kernel in non-secure" so that we can fake up the firmware-mandated reconfiguration only when we need it ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
173 lines
6.4 KiB
C
173 lines
6.4 KiB
C
/*
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* ARM GICv3 support - internal interfaces
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*
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* Copyright (c) 2012 Linaro Limited
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* Copyright (c) 2015 Huawei.
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Written by Peter Maydell
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* Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_ARM_GICV3_INTERNAL_H
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#define QEMU_ARM_GICV3_INTERNAL_H
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#include "hw/intc/arm_gicv3_common.h"
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/* Distributor registers, as offsets from the distributor base address */
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#define GICD_CTLR 0x0000
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#define GICD_TYPER 0x0004
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#define GICD_IIDR 0x0008
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#define GICD_STATUSR 0x0010
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#define GICD_SETSPI_NSR 0x0040
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#define GICD_CLRSPI_NSR 0x0048
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#define GICD_SETSPI_SR 0x0050
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#define GICD_CLRSPI_SR 0x0058
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#define GICD_SEIR 0x0068
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#define GICD_IGROUPR 0x0080
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#define GICD_ISENABLER 0x0100
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#define GICD_ICENABLER 0x0180
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#define GICD_ISPENDR 0x0200
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#define GICD_ICPENDR 0x0280
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#define GICD_ISACTIVER 0x0300
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#define GICD_ICACTIVER 0x0380
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#define GICD_IPRIORITYR 0x0400
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#define GICD_ITARGETSR 0x0800
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#define GICD_ICFGR 0x0C00
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#define GICD_IGRPMODR 0x0D00
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#define GICD_NSACR 0x0E00
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#define GICD_SGIR 0x0F00
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#define GICD_CPENDSGIR 0x0F10
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#define GICD_SPENDSGIR 0x0F20
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#define GICD_IROUTER 0x6000
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#define GICD_IDREGS 0xFFD0
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/* GICD_CTLR fields */
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#define GICD_CTLR_EN_GRP0 (1U << 0)
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#define GICD_CTLR_EN_GRP1NS (1U << 1) /* GICv3 5.3.20 */
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#define GICD_CTLR_EN_GRP1S (1U << 2)
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#define GICD_CTLR_EN_GRP1_ALL (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S)
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/* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */
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#define GICD_CTLR_ARE (1U << 4)
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#define GICD_CTLR_ARE_S (1U << 4)
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#define GICD_CTLR_ARE_NS (1U << 5)
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#define GICD_CTLR_DS (1U << 6)
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#define GICD_CTLR_E1NWF (1U << 7)
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#define GICD_CTLR_RWP (1U << 31)
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/*
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* Redistributor frame offsets from RD_base
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*/
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#define GICR_SGI_OFFSET 0x10000
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/*
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* Redistributor registers, offsets from RD_base
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*/
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#define GICR_CTLR 0x0000
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#define GICR_IIDR 0x0004
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#define GICR_TYPER 0x0008
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#define GICR_STATUSR 0x0010
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#define GICR_WAKER 0x0014
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#define GICR_SETLPIR 0x0040
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#define GICR_CLRLPIR 0x0048
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#define GICR_PROPBASER 0x0070
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#define GICR_PENDBASER 0x0078
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#define GICR_INVLPIR 0x00A0
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#define GICR_INVALLR 0x00B0
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#define GICR_SYNCR 0x00C0
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#define GICR_IDREGS 0xFFD0
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/* SGI and PPI Redistributor registers, offsets from RD_base */
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#define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080)
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#define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100)
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#define GICR_ICENABLER0 (GICR_SGI_OFFSET + 0x0180)
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#define GICR_ISPENDR0 (GICR_SGI_OFFSET + 0x0200)
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#define GICR_ICPENDR0 (GICR_SGI_OFFSET + 0x0280)
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#define GICR_ISACTIVER0 (GICR_SGI_OFFSET + 0x0300)
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#define GICR_ICACTIVER0 (GICR_SGI_OFFSET + 0x0380)
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#define GICR_IPRIORITYR (GICR_SGI_OFFSET + 0x0400)
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#define GICR_ICFGR0 (GICR_SGI_OFFSET + 0x0C00)
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#define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04)
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#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
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#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
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#define GICR_CTLR_ENABLE_LPIS (1U << 0)
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#define GICR_CTLR_RWP (1U << 3)
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#define GICR_CTLR_DPG0 (1U << 24)
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#define GICR_CTLR_DPG1NS (1U << 25)
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#define GICR_CTLR_DPG1S (1U << 26)
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#define GICR_CTLR_UWP (1U << 31)
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#define GICR_TYPER_PLPIS (1U << 0)
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#define GICR_TYPER_VLPIS (1U << 1)
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#define GICR_TYPER_DIRECTLPI (1U << 3)
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#define GICR_TYPER_LAST (1U << 4)
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#define GICR_TYPER_DPGS (1U << 5)
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#define GICR_TYPER_PROCNUM (0xFFFFU << 8)
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#define GICR_TYPER_COMMONLPIAFF (0x3 << 24)
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#define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32)
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#define GICR_WAKER_ProcessorSleep (1U << 1)
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#define GICR_WAKER_ChildrenAsleep (1U << 2)
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#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
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#define GICR_PROPBASER_ADDR_MASK (0xfffffffffULL << 12)
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#define GICR_PROPBASER_SHAREABILITY_MASK (3U << 10)
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#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
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#define GICR_PROPBASER_IDBITS_MASK (0x1f)
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#define GICR_PENDBASER_PTZ (1ULL << 62)
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#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
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#define GICR_PENDBASER_ADDR_MASK (0xffffffffULL << 16)
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#define GICR_PENDBASER_SHAREABILITY_MASK (3U << 10)
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#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
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#define ICC_CTLR_EL1_CBPR (1U << 0)
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#define ICC_CTLR_EL1_EOIMODE (1U << 1)
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#define ICC_CTLR_EL1_PMHE (1U << 6)
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#define ICC_CTLR_EL1_PRIBITS_SHIFT 8
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#define ICC_CTLR_EL1_IDBITS_SHIFT 11
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#define ICC_CTLR_EL1_SEIS (1U << 14)
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#define ICC_CTLR_EL1_A3V (1U << 15)
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#define ICC_PMR_PRIORITY_MASK 0xff
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#define ICC_BPR_BINARYPOINT_MASK 0x07
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#define ICC_IGRPEN_ENABLE 0x01
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#define ICC_CTLR_EL3_CBPR_EL1S (1U << 0)
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#define ICC_CTLR_EL3_CBPR_EL1NS (1U << 1)
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#define ICC_CTLR_EL3_EOIMODE_EL3 (1U << 2)
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#define ICC_CTLR_EL3_EOIMODE_EL1S (1U << 3)
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#define ICC_CTLR_EL3_EOIMODE_EL1NS (1U << 4)
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#define ICC_CTLR_EL3_RM (1U << 5)
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#define ICC_CTLR_EL3_PMHE (1U << 6)
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#define ICC_CTLR_EL3_PRIBITS_SHIFT 8
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#define ICC_CTLR_EL3_IDBITS_SHIFT 11
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#define ICC_CTLR_EL3_SEIS (1U << 14)
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#define ICC_CTLR_EL3_A3V (1U << 15)
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#define ICC_CTLR_EL3_NDS (1U << 17)
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/**
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* gicv3_redist_affid:
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*
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* Return the 32-bit affinity ID of the CPU connected to this redistributor
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*/
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static inline uint32_t gicv3_redist_affid(GICv3CPUState *cs)
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{
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return cs->gicr_typer >> 32;
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}
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#endif /* !QEMU_ARM_GIC_INTERNAL_H */
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