c300bbe8d2
Legacy PIC (8259) cannot be supported for TDX guests since TDX module doesn't allow directly interrupt injection. Using posted interrupts for the PIC is not a viable option as the guest BIOS/kernel will not do EOI for PIC IRQs, i.e. will leave the vIRR bit set. Make PIC the property of common x86 machine type. Hence all x86 machines, including microvm, can disable it. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-Id: <20220310122811.807794-3-xiaoyao.li@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
151 lines
4.8 KiB
C
151 lines
4.8 KiB
C
/*
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* Copyright (c) 2019 Red Hat, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_I386_X86_H
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#define HW_I386_X86_H
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#include "exec/hwaddr.h"
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#include "qemu/notify.h"
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#include "hw/i386/topology.h"
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#include "hw/boards.h"
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#include "hw/nmi.h"
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#include "hw/isa/isa.h"
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#include "hw/i386/ioapic.h"
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#include "qom/object.h"
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struct X86MachineClass {
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/*< private >*/
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MachineClass parent;
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/*< public >*/
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/* TSC rate migration: */
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bool save_tsc_khz;
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/* use DMA capable linuxboot option rom */
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bool fwcfg_dma_enabled;
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};
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struct X86MachineState {
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/*< private >*/
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MachineState parent;
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/*< public >*/
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/* Pointers to devices and objects: */
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ISADevice *rtc;
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FWCfgState *fw_cfg;
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qemu_irq *gsi;
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DeviceState *ioapic2;
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GMappedFile *initrd_mapped_file;
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HotplugHandler *acpi_dev;
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/* RAM information (sizes, addresses, configuration): */
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ram_addr_t below_4g_mem_size, above_4g_mem_size;
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/* CPU and apic information: */
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bool apic_xrupt_override;
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unsigned pci_irq_mask;
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unsigned apic_id_limit;
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uint16_t boot_cpus;
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SgxEPCList *sgx_epc_list;
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OnOffAuto smm;
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OnOffAuto acpi;
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OnOffAuto pit;
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OnOffAuto pic;
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char *oem_id;
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char *oem_table_id;
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/*
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* Address space used by IOAPIC device. All IOAPIC interrupts
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* will be translated to MSI messages in the address space.
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*/
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AddressSpace *ioapic_as;
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/*
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* Ratelimit enforced on detected bus locks in guest.
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* The default value of the bus_lock_ratelimit is 0 per second,
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* which means no limitation on the guest's bus locks.
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*/
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uint64_t bus_lock_ratelimit;
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};
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#define X86_MACHINE_SMM "smm"
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#define X86_MACHINE_ACPI "acpi"
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#define X86_MACHINE_PIT "pit"
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#define X86_MACHINE_PIC "pic"
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#define X86_MACHINE_OEM_ID "x-oem-id"
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#define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id"
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#define X86_MACHINE_BUS_LOCK_RATELIMIT "bus-lock-ratelimit"
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#define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
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OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)
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void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
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uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
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unsigned int cpu_index);
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void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp);
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void x86_cpus_init(X86MachineState *pcms, int default_cpu_version);
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CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
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unsigned cpu_index);
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int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
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const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
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CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx);
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void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count);
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void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp);
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void x86_cpu_plug(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp);
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void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp);
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void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp);
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void x86_bios_rom_init(MachineState *ms, const char *default_firmware,
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MemoryRegion *rom_memory, bool isapc_ram_fw);
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void x86_load_linux(X86MachineState *x86ms,
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FWCfgState *fw_cfg,
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int acpi_data_size,
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bool pvh_enabled);
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bool x86_machine_is_smm_enabled(const X86MachineState *x86ms);
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bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms);
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/* Global System Interrupts */
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#define GSI_NUM_PINS IOAPIC_NUM_PINS
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#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
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typedef struct GSIState {
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qemu_irq i8259_irq[ISA_NUM_IRQS];
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qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
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qemu_irq ioapic2_irq[IOAPIC_NUM_PINS];
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} GSIState;
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qemu_irq x86_allocate_cpu_irq(void);
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void gsi_handler(void *opaque, int n, int level);
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void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
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DeviceState *ioapic_init_secondary(GSIState *gsi_state);
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/* pc_sysfw.c */
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void x86_firmware_configure(void *ptr, int size);
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#endif
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