0762cd428f
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
346 lines
15 KiB
Plaintext
346 lines
15 KiB
Plaintext
# AArch64 SVE instruction descriptions
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#
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# Copyright (c) 2017 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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###########################################################################
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# Named fields. These are primarily for disjoint fields.
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%imm6_22_5 22:1 5:5
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%imm9_16_10 16:s6 10:3
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# A combination of tsz:imm3 -- extract esize.
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%tszimm_esz 22:2 5:5 !function=tszimm_esz
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# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
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%tszimm_shr 22:2 5:5 !function=tszimm_shr
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# A combination of tsz:imm3 -- extract (tsz:imm3) - esize
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%tszimm_shl 22:2 5:5 !function=tszimm_shl
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# Similarly for the tszh/tszl pair at 22/16 for zzi
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%tszimm16_esz 22:2 16:5 !function=tszimm_esz
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%tszimm16_shr 22:2 16:5 !function=tszimm_shr
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%tszimm16_shl 22:2 16:5 !function=tszimm_shl
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# Either a copy of rd (at bit 0), or a different source
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# as propagated via the MOVPRFX instruction.
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%reg_movprfx 0:5
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###########################################################################
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# Named attribute sets. These are used to make nice(er) names
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# when creating helpers common to those for the individual
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# instruction patterns.
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&rr_esz rd rn esz
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&rri rd rn imm
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&rrri rd rn rm imm
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&rri_esz rd rn imm esz
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&rrr_esz rd rn rm esz
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&rpr_esz rd pg rn esz
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&rprr_s rd pg rn rm s
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&rprr_esz rd pg rn rm esz
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&rprrr_esz rd pg rn rm ra esz
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&rpri_esz rd pg rn imm esz
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###########################################################################
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# Named instruction formats. These are generally used to
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# reduce the amount of duplication between instruction patterns.
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# Two operand with unused vector element size
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@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
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# Two operand
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@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
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@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
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# Three operand with unused vector element size
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@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
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# Three predicate operand, with governing predicate, flag setting
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@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
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# Three operand, vector element size
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@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
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# Three operand with "memory" size, aka immediate left shift
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@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
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# Two register operand, with governing predicate, vector element size
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@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
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&rprr_esz rn=%reg_movprfx
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@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
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&rprr_esz rm=%reg_movprfx
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# Three register operand, with governing predicate, vector element size
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@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
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&rprrr_esz ra=%reg_movprfx
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@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
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&rprrr_esz rn=%reg_movprfx
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# One register operand, with governing predicate, vector element size
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@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
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# Two register operands with a 6-bit signed immediate.
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@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
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# Two register operand, one immediate operand, with predicate,
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# element size encoded as TSZHL. User must fill in imm.
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@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
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&rpri_esz rn=%reg_movprfx esz=%tszimm_esz
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# Similarly without predicate.
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@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
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&rri_esz esz=%tszimm16_esz
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# Basic Load/Store with 9-bit immediate offset
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@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
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&rri imm=%imm9_16_10
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@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
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&rri imm=%imm9_16_10
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###########################################################################
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# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
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### SVE Integer Arithmetic - Binary Predicated Group
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# SVE bitwise logical vector operations (predicated)
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ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
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EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
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AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
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BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
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# SVE integer add/subtract vectors (predicated)
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ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
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SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
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SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
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# SVE integer min/max/difference (predicated)
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SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
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UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
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SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
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UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
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SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
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UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
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# SVE integer multiply/divide (predicated)
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MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
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SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
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UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
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# Note that divide requires size >= 2; below 2 is unallocated.
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SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
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UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
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SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
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UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
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### SVE Integer Reduction Group
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# SVE bitwise logical reduction (predicated)
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ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
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EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
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ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
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# SVE integer add reduction (predicated)
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# Note that saddv requires size != 3.
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UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
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SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
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# SVE integer min/max reduction (predicated)
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SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
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UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
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SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
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UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
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### SVE Shift by Immediate - Predicated Group
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# SVE bitwise shift by immediate (predicated)
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ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
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@rdn_pg_tszimm imm=%tszimm_shr
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LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
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@rdn_pg_tszimm imm=%tszimm_shr
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LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
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@rdn_pg_tszimm imm=%tszimm_shl
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ASRD 00000100 .. 000 100 100 ... .. ... ..... \
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@rdn_pg_tszimm imm=%tszimm_shr
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# SVE bitwise shift by vector (predicated)
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ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
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LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
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LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
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ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
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LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
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LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
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# SVE bitwise shift by wide elements (predicated)
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# Note these require size != 3.
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ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
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LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
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LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
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### SVE Integer Arithmetic - Unary Predicated Group
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# SVE unary bit operations (predicated)
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# Note esz != 0 for FABS and FNEG.
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CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
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CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
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CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
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CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
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NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
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FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
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FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
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# SVE integer unary operations (predicated)
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# Note esz > original size for extensions.
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ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
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NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
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SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
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UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
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SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
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UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
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SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
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UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
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### SVE Integer Multiply-Add Group
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# SVE integer multiply-add writing addend (predicated)
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MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
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MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
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# SVE integer multiply-add writing multiplicand (predicated)
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MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
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MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
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### SVE Integer Arithmetic - Unpredicated Group
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# SVE integer add/subtract vectors (unpredicated)
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ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
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SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
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SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
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UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
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SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
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UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
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### SVE Logical - Unpredicated Group
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# SVE bitwise logical operations (unpredicated)
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AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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### SVE Index Generation Group
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# SVE index generation (immediate start, immediate increment)
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INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
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# SVE index generation (immediate start, register increment)
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INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
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# SVE index generation (register start, immediate increment)
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INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
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# SVE index generation (register start, register increment)
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INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
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### SVE Stack Allocation Group
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# SVE stack frame adjustment
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ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
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ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
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# SVE stack frame size
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RDVL 00000100 101 11111 01010 imm:s6 rd:5
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### SVE Bitwise Shift - Unpredicated Group
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# SVE bitwise shift by immediate (unpredicated)
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ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
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@rd_rn_tszimm imm=%tszimm16_shr
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LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
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@rd_rn_tszimm imm=%tszimm16_shr
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LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
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@rd_rn_tszimm imm=%tszimm16_shl
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# SVE bitwise shift by wide elements (unpredicated)
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# Note esz != 3
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ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
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LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
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LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
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### SVE Compute Vector Address Group
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# SVE vector address generation
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ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
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ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
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ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
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ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
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### SVE Integer Misc - Unpredicated Group
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# SVE floating-point exponential accelerator
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# Note esz != 0
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FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
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### SVE Predicate Logical Operations Group
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# SVE predicate logical operations
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AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
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BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
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EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
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SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
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ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
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ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
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NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
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NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
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### SVE Predicate Misc Group
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# SVE predicate test
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PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
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# SVE predicate initialize
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PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
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# SVE initialize FFR
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SETFFR 00100101 0010 1100 1001 0000 0000 0000
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# SVE zero predicate register
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PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
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# SVE predicate read from FFR (predicated)
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RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
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# SVE predicate read from FFR (unpredicated)
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RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
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# SVE FFR write from predicate (WRFFR)
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WRFFR 00100101 0010 1000 1001 000 rn:4 00000
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# SVE predicate first active
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PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
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# SVE predicate next active
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PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
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### SVE Memory - 32-bit Gather and Unsized Contiguous Group
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# SVE load predicate register
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LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
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# SVE load vector register
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LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
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