0722d05ad8
The OCC is an on-chip microcontroller based on a ppc405 core used for various power management tasks. It comes with a pile of additional hardware sitting on the PIB (aka XSCOM bus). At this point we don't emulate it (nor plan to do so). However there is one facility which is provided by the surrounding hardware that we do need, which is the interrupt generation facility. OPAL uses it to send itself interrupts under some circumstances and there are other uses around the corner. So this implement just enough to support this. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: - updated for qemu-2.9 - changed the XSCOM interface to fit new model - QOMified the model ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> |
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fdt.h | ||
mac_dbdma.h | ||
openpic.h | ||
pnv_core.h | ||
pnv_lpc.h | ||
pnv_occ.h | ||
pnv_psi.h | ||
pnv_xscom.h | ||
pnv.h | ||
ppc4xx.h | ||
ppc_e500.h | ||
ppc.h | ||
spapr_cpu_core.h | ||
spapr_drc.h | ||
spapr_ovec.h | ||
spapr_rtas.h | ||
spapr_vio.h | ||
spapr.h | ||
xics.h |