Michael Clark 426f03482c RISC-V: Update CSR and interrupt definitions ... * Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. * Remove erroneous until comments on machine mode interrupts. * Move together paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-10-17 13:02:19 -07:00
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cpu_bits.h	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
cpu_helper.c	RISC-V: Move non-ops from op_helper to cpu_helper	2018-10-17 13:02:14 -07:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
cpu.h	RISC-V: Allow setting and clearing multiple irqs	2018-10-17 13:02:09 -07:00
fpu_helper.c	target/riscv: Remove floatX_maybe_silence_nan from conversions	2018-05-17 15:27:15 -07:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V: Move non-ops from op_helper to cpu_helper	2018-10-17 13:02:14 -07:00
op_helper.c	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
pmp.c	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	target/riscv: call gen_goto_tb on DISAS_TOO_MANY	2018-09-05 09:58:38 -07:00