a30c34d2ab
Rather than looking inside the definition of a DeviceState with "s->qdev", use the QOM prefered style: "DEVICE(s)". This patch was generated using the following Coccinelle script: // Use DEVICE() macros to access DeviceState.qdev @use_device_macro_to_access_qdev@ expression obj; identifier dev; @@ -&obj->dev.qdev +DEVICE(obj) Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20190528164020.32250-8-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
826 lines
24 KiB
C
826 lines
24 KiB
C
/*
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* QEMU ICH9 Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2009, 2010, 2011
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* Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This is based on piix.c, but heavily modified.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "qapi/visitor.h"
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#include "qemu/range.h"
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#include "hw/isa/isa.h"
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#include "hw/sysbus.h"
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#include "hw/i386/pc.h"
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#include "hw/isa/apm.h"
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#include "hw/i386/ioapic.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/i386/ich9.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/ich9.h"
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#include "hw/pci/pci_bus.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "qom/cpu.h"
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#include "hw/nvram/fw_cfg.h"
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#include "qemu/cutils.h"
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/*****************************************************************************/
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/* ICH9 LPC PCI to ISA bridge */
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static void ich9_lpc_reset(DeviceState *qdev);
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/* chipset configuration register
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* to access chipset configuration registers, pci_[sg]et_{byte, word, long}
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* are used.
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* Although it's not pci configuration space, it's little endian as Intel.
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*/
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static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
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{
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int intx;
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for (intx = 0; intx < PCI_NUM_PINS; intx++) {
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irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
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}
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}
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static void ich9_cc_update(ICH9LPCState *lpc)
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{
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int slot;
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int pci_intx;
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const int reg_offsets[] = {
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ICH9_CC_D25IR,
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ICH9_CC_D26IR,
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ICH9_CC_D27IR,
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ICH9_CC_D28IR,
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ICH9_CC_D29IR,
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ICH9_CC_D30IR,
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ICH9_CC_D31IR,
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};
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const int *offset;
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/* D{25 - 31}IR, but D30IR is read only to 0. */
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for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
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if (slot == 30) {
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continue;
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}
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ich9_cc_update_ir(lpc->irr[slot],
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pci_get_word(lpc->chip_config + *offset));
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}
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/*
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* D30: DMI2PCI bridge
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* It is arbitrarily decided how INTx lines of PCI devices behind
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* the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
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* INT[A-D] are connected to PIRQ[E-H]
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*/
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for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
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lpc->irr[30][pci_intx] = pci_intx + 4;
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}
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}
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static void ich9_cc_init(ICH9LPCState *lpc)
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{
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int slot;
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int intx;
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/* the default irq routing is arbitrary as long as it matches with
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* acpi irq routing table.
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* The one that is incompatible with piix_pci(= bochs) one is
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* intentionally chosen to let the users know that the different
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* board is used.
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*
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* int[A-D] -> pirq[E-F]
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* avoid pirq A-D because they are used for pci express port
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*/
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for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
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for (intx = 0; intx < PCI_NUM_PINS; intx++) {
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lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
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}
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}
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ich9_cc_update(lpc);
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}
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static void ich9_cc_reset(ICH9LPCState *lpc)
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{
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uint8_t *c = lpc->chip_config;
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memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
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pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
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pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
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pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
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ich9_cc_update(lpc);
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}
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static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
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{
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*addr &= ICH9_CC_ADDR_MASK;
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if (*addr + *len >= ICH9_CC_SIZE) {
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*len = ICH9_CC_SIZE - *addr;
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}
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}
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/* val: little endian */
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static void ich9_cc_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned len)
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{
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ICH9LPCState *lpc = (ICH9LPCState *)opaque;
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ich9_cc_addr_len(&addr, &len);
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memcpy(lpc->chip_config + addr, &val, len);
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pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
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ich9_cc_update(lpc);
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}
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/* return value: little endian */
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static uint64_t ich9_cc_read(void *opaque, hwaddr addr,
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unsigned len)
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{
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ICH9LPCState *lpc = (ICH9LPCState *)opaque;
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uint32_t val = 0;
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ich9_cc_addr_len(&addr, &len);
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memcpy(&val, lpc->chip_config + addr, len);
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return val;
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}
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/* IRQ routing */
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/* */
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static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
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{
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*pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
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*pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
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}
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static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num,
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int *pic_irq, int *pic_dis)
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{
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switch (pirq_num) {
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case 0 ... 3: /* A-D */
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ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num],
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pic_irq, pic_dis);
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return;
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case 4 ... 7: /* E-H */
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ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)],
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pic_irq, pic_dis);
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return;
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default:
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break;
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}
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abort();
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}
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/* gsi: i8259+ioapic irq 0-15, otherwise assert */
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static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi)
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{
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int i, pic_level;
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assert(gsi < ICH9_LPC_PIC_NUM_PINS);
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/* The pic level is the logical OR of all the PCI irqs mapped to it */
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pic_level = 0;
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for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
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int tmp_irq;
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int tmp_dis;
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ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
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if (!tmp_dis && tmp_irq == gsi) {
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pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i);
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}
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}
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if (gsi == lpc->sci_gsi) {
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pic_level |= lpc->sci_level;
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}
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qemu_set_irq(lpc->gsi[gsi], pic_level);
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}
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/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
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static int ich9_pirq_to_gsi(int pirq)
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{
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return pirq + ICH9_LPC_PIC_NUM_PINS;
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}
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static int ich9_gsi_to_pirq(int gsi)
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{
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return gsi - ICH9_LPC_PIC_NUM_PINS;
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}
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/* gsi: ioapic irq 16-23, otherwise assert */
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static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
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{
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int level = 0;
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assert(gsi >= ICH9_LPC_PIC_NUM_PINS);
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level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi));
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if (gsi == lpc->sci_gsi) {
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level |= lpc->sci_level;
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}
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qemu_set_irq(lpc->gsi[gsi], level);
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}
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void ich9_lpc_set_irq(void *opaque, int pirq, int level)
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{
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ICH9LPCState *lpc = opaque;
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int pic_irq, pic_dis;
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assert(0 <= pirq);
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assert(pirq < ICH9_LPC_NB_PIRQS);
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ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq));
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ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
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ich9_lpc_update_pic(lpc, pic_irq);
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}
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/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
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* a given device irq pin.
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*/
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int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
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{
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BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
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PCIBus *pci_bus = PCI_BUS(bus);
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PCIDevice *lpc_pdev =
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pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)];
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ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev);
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return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
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}
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PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
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{
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ICH9LPCState *lpc = opaque;
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PCIINTxRoute route;
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int pic_irq;
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int pic_dis;
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assert(0 <= pirq_pin);
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assert(pirq_pin < ICH9_LPC_NB_PIRQS);
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route.mode = PCI_INTX_ENABLED;
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ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis);
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if (!pic_dis) {
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if (pic_irq < ICH9_LPC_PIC_NUM_PINS) {
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route.irq = pic_irq;
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} else {
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route.mode = PCI_INTX_DISABLED;
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route.irq = -1;
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}
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} else {
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route.irq = ich9_pirq_to_gsi(pirq_pin);
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}
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return route;
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}
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void ich9_generate_smi(void)
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{
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cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
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}
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static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
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{
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switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
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ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
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case ICH9_LPC_ACPI_CTRL_9:
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return 9;
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case ICH9_LPC_ACPI_CTRL_10:
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return 10;
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case ICH9_LPC_ACPI_CTRL_11:
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return 11;
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case ICH9_LPC_ACPI_CTRL_20:
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return 20;
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case ICH9_LPC_ACPI_CTRL_21:
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return 21;
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default:
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/* reserved */
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break;
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}
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return -1;
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}
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static void ich9_set_sci(void *opaque, int irq_num, int level)
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{
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ICH9LPCState *lpc = opaque;
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int irq;
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assert(irq_num == 0);
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level = !!level;
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if (level == lpc->sci_level) {
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return;
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}
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lpc->sci_level = level;
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irq = lpc->sci_gsi;
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if (irq < 0) {
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return;
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}
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if (irq >= ICH9_LPC_PIC_NUM_PINS) {
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ich9_lpc_update_apic(lpc, irq);
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} else {
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ich9_lpc_update_pic(lpc, irq);
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}
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}
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static void smi_features_ok_callback(void *opaque)
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{
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ICH9LPCState *lpc = opaque;
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uint64_t guest_features;
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if (lpc->smi_features_ok) {
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/* negotiation already complete, features locked */
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return;
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}
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memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features);
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le64_to_cpus(&guest_features);
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if (guest_features & ~lpc->smi_host_features) {
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/* guest requests invalid features, leave @features_ok at zero */
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return;
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}
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/* valid feature subset requested, lock it down, report success */
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lpc->smi_negotiated_features = guest_features;
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lpc->smi_features_ok = 1;
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}
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void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
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{
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ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
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qemu_irq sci_irq;
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FWCfgState *fw_cfg = fw_cfg_find();
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sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
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ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
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if (lpc->smi_host_features && fw_cfg) {
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uint64_t host_features_le;
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host_features_le = cpu_to_le64(lpc->smi_host_features);
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memcpy(lpc->smi_host_features_le, &host_features_le,
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sizeof host_features_le);
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fw_cfg_add_file(fw_cfg, "etc/smi/supported-features",
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lpc->smi_host_features_le,
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sizeof lpc->smi_host_features_le);
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/* The other two guest-visible fields are cleared on device reset, we
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* just link them into fw_cfg here.
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*/
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fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features",
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NULL, NULL, NULL,
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lpc->smi_guest_features_le,
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sizeof lpc->smi_guest_features_le,
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false);
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fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok",
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smi_features_ok_callback, NULL, lpc,
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&lpc->smi_features_ok,
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sizeof lpc->smi_features_ok,
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true);
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}
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ich9_lpc_reset(DEVICE(lpc));
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}
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|
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/* APM */
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|
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static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
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{
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ICH9LPCState *lpc = arg;
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|
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/* ACPI specs 3.0, 4.7.2.5 */
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acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
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val == ICH9_APM_ACPI_ENABLE,
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val == ICH9_APM_ACPI_DISABLE);
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if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) {
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return;
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}
|
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|
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/* SMI_EN = PMBASE + 30. SMI control and enable register */
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if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
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if (lpc->smi_negotiated_features &
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(UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) {
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CPUState *cs;
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CPU_FOREACH(cs) {
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cpu_interrupt(cs, CPU_INTERRUPT_SMI);
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}
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} else {
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cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI);
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}
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}
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}
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|
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/* config:PMBASE */
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static void
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ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc)
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{
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uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
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uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL);
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uint8_t new_gsi;
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|
|
if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) {
|
|
pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
|
|
} else {
|
|
pm_io_base = 0;
|
|
}
|
|
|
|
ich9_pm_iospace_update(&lpc->pm, pm_io_base);
|
|
|
|
new_gsi = ich9_lpc_sci_irq(lpc);
|
|
if (lpc->sci_level && new_gsi != lpc->sci_gsi) {
|
|
qemu_set_irq(lpc->pm.irq, 0);
|
|
lpc->sci_gsi = new_gsi;
|
|
qemu_set_irq(lpc->pm.irq, 1);
|
|
}
|
|
lpc->sci_gsi = new_gsi;
|
|
}
|
|
|
|
/* config:RCBA */
|
|
static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old)
|
|
{
|
|
uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
|
|
|
|
if (rcba_old & ICH9_LPC_RCBA_EN) {
|
|
memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem);
|
|
}
|
|
if (rcba & ICH9_LPC_RCBA_EN) {
|
|
memory_region_add_subregion_overlap(get_system_memory(),
|
|
rcba & ICH9_LPC_RCBA_BA_MASK,
|
|
&lpc->rcrb_mem, 1);
|
|
}
|
|
}
|
|
|
|
/* config:GEN_PMCON* */
|
|
static void
|
|
ich9_lpc_pmcon_update(ICH9LPCState *lpc)
|
|
{
|
|
uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1);
|
|
uint16_t wmask;
|
|
|
|
if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) {
|
|
wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1);
|
|
wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK;
|
|
pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask);
|
|
lpc->pm.smi_en_wmask &= ~1;
|
|
}
|
|
}
|
|
|
|
static int ich9_lpc_post_load(void *opaque, int version_id)
|
|
{
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
ich9_lpc_pmbase_sci_update(lpc);
|
|
ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */);
|
|
ich9_lpc_pmcon_update(lpc);
|
|
return 0;
|
|
}
|
|
|
|
static void ich9_lpc_config_write(PCIDevice *d,
|
|
uint32_t addr, uint32_t val, int len)
|
|
{
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
|
|
uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
|
|
|
|
pci_default_write_config(d, addr, val, len);
|
|
if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) ||
|
|
ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) {
|
|
ich9_lpc_pmbase_sci_update(lpc);
|
|
}
|
|
if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
|
|
ich9_lpc_rcba_update(lpc, rcba_old);
|
|
}
|
|
if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) {
|
|
pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
|
|
}
|
|
if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
|
|
pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
|
|
}
|
|
if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) {
|
|
ich9_lpc_pmcon_update(lpc);
|
|
}
|
|
}
|
|
|
|
static void ich9_lpc_reset(DeviceState *qdev)
|
|
{
|
|
PCIDevice *d = PCI_DEVICE(qdev);
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
|
|
uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
|
|
int i;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
|
|
ICH9_LPC_PIRQ_ROUT_DEFAULT);
|
|
}
|
|
for (i = 0; i < 4; i++) {
|
|
pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
|
|
ICH9_LPC_PIRQ_ROUT_DEFAULT);
|
|
}
|
|
pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
|
|
|
|
pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
|
|
pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
|
|
|
|
ich9_cc_reset(lpc);
|
|
|
|
ich9_lpc_pmbase_sci_update(lpc);
|
|
ich9_lpc_rcba_update(lpc, rcba_old);
|
|
|
|
lpc->sci_level = 0;
|
|
lpc->rst_cnt = 0;
|
|
|
|
memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le);
|
|
lpc->smi_features_ok = 0;
|
|
lpc->smi_negotiated_features = 0;
|
|
}
|
|
|
|
/* root complex register block is mapped into memory space */
|
|
static const MemoryRegionOps rcrb_mmio_ops = {
|
|
.read = ich9_cc_read,
|
|
.write = ich9_cc_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
|
|
{
|
|
ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
|
|
MemoryRegion *io_as = pci_address_space_io(&s->d);
|
|
uint8_t *pci_conf;
|
|
|
|
pci_conf = s->d.config;
|
|
if (memory_region_present(io_as, 0x3f8)) {
|
|
/* com1 */
|
|
pci_conf[0x82] |= 0x01;
|
|
}
|
|
if (memory_region_present(io_as, 0x2f8)) {
|
|
/* com2 */
|
|
pci_conf[0x82] |= 0x02;
|
|
}
|
|
if (memory_region_present(io_as, 0x378)) {
|
|
/* lpt */
|
|
pci_conf[0x82] |= 0x04;
|
|
}
|
|
if (memory_region_present(io_as, 0x3f2)) {
|
|
/* floppy */
|
|
pci_conf[0x82] |= 0x08;
|
|
}
|
|
}
|
|
|
|
/* reset control */
|
|
static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val,
|
|
unsigned len)
|
|
{
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
if (val & 4) {
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
|
return;
|
|
}
|
|
lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
|
|
}
|
|
|
|
static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len)
|
|
{
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
return lpc->rst_cnt;
|
|
}
|
|
|
|
static const MemoryRegionOps ich9_rst_cnt_ops = {
|
|
.read = ich9_rst_cnt_read,
|
|
.write = ich9_rst_cnt_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN
|
|
};
|
|
|
|
static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
|
|
uint32_t value = lpc->sci_gsi;
|
|
|
|
visit_type_uint32(v, name, &value, errp);
|
|
}
|
|
|
|
static void ich9_lpc_add_properties(ICH9LPCState *lpc)
|
|
{
|
|
static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
|
|
static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
|
|
|
|
object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32",
|
|
ich9_lpc_get_sci_int,
|
|
NULL, NULL, NULL, NULL);
|
|
object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
|
|
&acpi_enable_cmd, NULL);
|
|
object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
|
|
&acpi_disable_cmd, NULL);
|
|
|
|
ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL);
|
|
}
|
|
|
|
static void ich9_lpc_initfn(Object *obj)
|
|
{
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
|
|
|
|
ich9_lpc_add_properties(lpc);
|
|
}
|
|
|
|
static void ich9_lpc_realize(PCIDevice *d, Error **errp)
|
|
{
|
|
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
|
|
DeviceState *dev = DEVICE(d);
|
|
ISABus *isa_bus;
|
|
|
|
isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(),
|
|
errp);
|
|
if (!isa_bus) {
|
|
return;
|
|
}
|
|
|
|
pci_set_long(d->wmask + ICH9_LPC_PMBASE,
|
|
ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
|
|
pci_set_byte(d->wmask + ICH9_LPC_PMBASE,
|
|
ICH9_LPC_ACPI_CTRL_ACPI_EN |
|
|
ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK);
|
|
|
|
memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
|
|
"lpc-rcrb-mmio", ICH9_CC_SIZE);
|
|
|
|
lpc->isa_bus = isa_bus;
|
|
|
|
ich9_cc_init(lpc);
|
|
apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
|
|
|
|
lpc->machine_ready.notify = ich9_lpc_machine_ready;
|
|
qemu_add_machine_init_done_notifier(&lpc->machine_ready);
|
|
|
|
memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc,
|
|
"lpc-reset-control", 1);
|
|
memory_region_add_subregion_overlap(pci_address_space_io(d),
|
|
ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
|
|
1);
|
|
|
|
qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
|
|
|
|
isa_bus_irqs(isa_bus, lpc->gsi);
|
|
}
|
|
|
|
static bool ich9_rst_cnt_needed(void *opaque)
|
|
{
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
return (lpc->rst_cnt != 0);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_ich9_rst_cnt = {
|
|
.name = "ICH9LPC/rst_cnt",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = ich9_rst_cnt_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT8(rst_cnt, ICH9LPCState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool ich9_smi_feat_needed(void *opaque)
|
|
{
|
|
ICH9LPCState *lpc = opaque;
|
|
|
|
return !buffer_is_zero(lpc->smi_guest_features_le,
|
|
sizeof lpc->smi_guest_features_le) ||
|
|
lpc->smi_features_ok;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_ich9_smi_feat = {
|
|
.name = "ICH9LPC/smi_feat",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = ich9_smi_feat_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState,
|
|
sizeof(uint64_t)),
|
|
VMSTATE_UINT8(smi_features_ok, ICH9LPCState),
|
|
VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_ich9_lpc = {
|
|
.name = "ICH9LPC",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.post_load = ich9_lpc_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_PCI_DEVICE(d, ICH9LPCState),
|
|
VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState),
|
|
VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs),
|
|
VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE),
|
|
VMSTATE_UINT32(sci_level, ICH9LPCState),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
.subsections = (const VMStateDescription*[]) {
|
|
&vmstate_ich9_rst_cnt,
|
|
&vmstate_ich9_smi_feat,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
static Property ich9_lpc_properties[] = {
|
|
DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true),
|
|
DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
|
|
ICH9_LPC_SMI_F_BROADCAST_BIT, true),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
|
|
{
|
|
ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
|
|
|
|
acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev);
|
|
}
|
|
|
|
static void ich9_lpc_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
|
|
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
|
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
dc->reset = ich9_lpc_reset;
|
|
k->realize = ich9_lpc_realize;
|
|
dc->vmsd = &vmstate_ich9_lpc;
|
|
dc->props = ich9_lpc_properties;
|
|
k->config_write = ich9_lpc_config_write;
|
|
dc->desc = "ICH9 LPC bridge";
|
|
k->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
|
|
k->revision = ICH9_A2_LPC_REVISION;
|
|
k->class_id = PCI_CLASS_BRIDGE_ISA;
|
|
/*
|
|
* Reason: part of ICH9 southbridge, needs to be wired up by
|
|
* pc_q35_init()
|
|
*/
|
|
dc->user_creatable = false;
|
|
hc->pre_plug = ich9_pm_device_pre_plug_cb;
|
|
hc->plug = ich9_pm_device_plug_cb;
|
|
hc->unplug_request = ich9_pm_device_unplug_request_cb;
|
|
hc->unplug = ich9_pm_device_unplug_cb;
|
|
adevc->ospm_status = ich9_pm_ospm_status;
|
|
adevc->send_event = ich9_send_gpe;
|
|
adevc->madt_cpu = pc_madt_cpu_entry;
|
|
}
|
|
|
|
static const TypeInfo ich9_lpc_info = {
|
|
.name = TYPE_ICH9_LPC_DEVICE,
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(struct ICH9LPCState),
|
|
.instance_init = ich9_lpc_initfn,
|
|
.class_init = ich9_lpc_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_HOTPLUG_HANDLER },
|
|
{ TYPE_ACPI_DEVICE_IF },
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void ich9_lpc_register(void)
|
|
{
|
|
type_register_static(&ich9_lpc_info);
|
|
}
|
|
|
|
type_init(ich9_lpc_register);
|