9f61763574
Add a model of the Xilinx Versal Accelerator RAM (XRAM). This is mainly a stub to make firmware happy. The size of the RAMs can be probed. The interrupt mask logic is modelled but none of the interrups will ever be raised unless injected. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210308224637.2949533-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* QEMU model of the Xilinx XRAM Controller.
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*
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* Copyright (c) 2021 Xilinx Inc.
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*/
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#ifndef XLNX_VERSAL_XRAMC_H
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#define XLNX_VERSAL_XRAMC_H
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#define TYPE_XLNX_XRAM_CTRL "xlnx.versal-xramc"
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#define XLNX_XRAM_CTRL(obj) \
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OBJECT_CHECK(XlnxXramCtrl, (obj), TYPE_XLNX_XRAM_CTRL)
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REG32(XRAM_ERR_CTRL, 0x0)
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FIELD(XRAM_ERR_CTRL, UE_RES, 3, 1)
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FIELD(XRAM_ERR_CTRL, PWR_ERR_RES, 2, 1)
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FIELD(XRAM_ERR_CTRL, PZ_ERR_RES, 1, 1)
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FIELD(XRAM_ERR_CTRL, APB_ERR_RES, 0, 1)
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REG32(XRAM_ISR, 0x4)
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FIELD(XRAM_ISR, INV_APB, 0, 1)
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REG32(XRAM_IMR, 0x8)
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FIELD(XRAM_IMR, INV_APB, 0, 1)
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REG32(XRAM_IEN, 0xc)
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FIELD(XRAM_IEN, INV_APB, 0, 1)
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REG32(XRAM_IDS, 0x10)
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FIELD(XRAM_IDS, INV_APB, 0, 1)
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REG32(XRAM_ECC_CNTL, 0x14)
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FIELD(XRAM_ECC_CNTL, FI_MODE, 2, 1)
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FIELD(XRAM_ECC_CNTL, DET_ONLY, 1, 1)
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FIELD(XRAM_ECC_CNTL, ECC_ON_OFF, 0, 1)
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REG32(XRAM_CLR_EXE, 0x18)
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FIELD(XRAM_CLR_EXE, MON_7, 7, 1)
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FIELD(XRAM_CLR_EXE, MON_6, 6, 1)
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FIELD(XRAM_CLR_EXE, MON_5, 5, 1)
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FIELD(XRAM_CLR_EXE, MON_4, 4, 1)
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FIELD(XRAM_CLR_EXE, MON_3, 3, 1)
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FIELD(XRAM_CLR_EXE, MON_2, 2, 1)
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FIELD(XRAM_CLR_EXE, MON_1, 1, 1)
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FIELD(XRAM_CLR_EXE, MON_0, 0, 1)
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REG32(XRAM_CE_FFA, 0x1c)
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FIELD(XRAM_CE_FFA, ADDR, 0, 20)
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REG32(XRAM_CE_FFD0, 0x20)
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REG32(XRAM_CE_FFD1, 0x24)
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REG32(XRAM_CE_FFD2, 0x28)
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REG32(XRAM_CE_FFD3, 0x2c)
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REG32(XRAM_CE_FFE, 0x30)
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FIELD(XRAM_CE_FFE, SYNDROME, 0, 16)
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REG32(XRAM_UE_FFA, 0x34)
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FIELD(XRAM_UE_FFA, ADDR, 0, 20)
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REG32(XRAM_UE_FFD0, 0x38)
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REG32(XRAM_UE_FFD1, 0x3c)
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REG32(XRAM_UE_FFD2, 0x40)
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REG32(XRAM_UE_FFD3, 0x44)
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REG32(XRAM_UE_FFE, 0x48)
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FIELD(XRAM_UE_FFE, SYNDROME, 0, 16)
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REG32(XRAM_FI_D0, 0x4c)
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REG32(XRAM_FI_D1, 0x50)
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REG32(XRAM_FI_D2, 0x54)
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REG32(XRAM_FI_D3, 0x58)
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REG32(XRAM_FI_SY, 0x5c)
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FIELD(XRAM_FI_SY, DATA, 0, 16)
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REG32(XRAM_RMW_UE_FFA, 0x70)
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FIELD(XRAM_RMW_UE_FFA, ADDR, 0, 20)
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REG32(XRAM_FI_CNTR, 0x74)
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FIELD(XRAM_FI_CNTR, COUNT, 0, 24)
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REG32(XRAM_IMP, 0x80)
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FIELD(XRAM_IMP, SIZE, 0, 4)
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REG32(XRAM_PRDY_DBG, 0x84)
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FIELD(XRAM_PRDY_DBG, ISLAND3, 12, 4)
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FIELD(XRAM_PRDY_DBG, ISLAND2, 8, 4)
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FIELD(XRAM_PRDY_DBG, ISLAND1, 4, 4)
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FIELD(XRAM_PRDY_DBG, ISLAND0, 0, 4)
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REG32(XRAM_SAFETY_CHK, 0xff8)
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#define XRAM_CTRL_R_MAX (R_XRAM_SAFETY_CHK + 1)
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typedef struct XlnxXramCtrl {
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SysBusDevice parent_obj;
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MemoryRegion ram;
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qemu_irq irq;
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struct {
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uint64_t size;
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unsigned int encoded_size;
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} cfg;
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RegisterInfoArray *reg_array;
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uint32_t regs[XRAM_CTRL_R_MAX];
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RegisterInfo regs_info[XRAM_CTRL_R_MAX];
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} XlnxXramCtrl;
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#endif
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