b2580720d0
Replace Monitor API by HumanReadableText one (see commit f2de406f29
"docs/devel: document expectations for QAPI data modelling for QMP"
for rationale).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20240610063518.50680-2-philmd@linaro.org>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* QEMU Motorola 680x0 IRQ Controller
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*
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* (c) 2020 Laurent Vivier <laurent@vivier.eu>
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*
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "hw/nmi.h"
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#include "hw/intc/intc.h"
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#include "hw/intc/m68k_irqc.h"
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static bool m68k_irqc_get_statistics(InterruptStatsProvider *obj,
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uint64_t **irq_counts, unsigned int *nb_irqs)
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{
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M68KIRQCState *s = M68K_IRQC(obj);
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*irq_counts = s->stats_irq_count;
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*nb_irqs = ARRAY_SIZE(s->stats_irq_count);
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return true;
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}
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static void m68k_irqc_print_info(InterruptStatsProvider *obj, GString *buf)
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{
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M68KIRQCState *s = M68K_IRQC(obj);
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g_string_append_printf(buf, "m68k-irqc: ipr=0x%x\n", s->ipr);
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}
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static void m68k_set_irq(void *opaque, int irq, int level)
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{
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M68KIRQCState *s = opaque;
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M68kCPU *cpu = M68K_CPU(s->cpu);
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int i;
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if (level) {
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s->ipr |= 1 << irq;
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s->stats_irq_count[irq]++;
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} else {
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s->ipr &= ~(1 << irq);
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}
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for (i = M68K_IRQC_LEVEL_7; i >= M68K_IRQC_LEVEL_1; i--) {
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if ((s->ipr >> i) & 1) {
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m68k_set_irq_level(cpu, i + 1, i + M68K_IRQC_AUTOVECTOR_BASE);
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return;
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}
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}
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m68k_set_irq_level(cpu, 0, 0);
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}
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static void m68k_irqc_reset(DeviceState *d)
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{
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M68KIRQCState *s = M68K_IRQC(d);
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int i;
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s->ipr = 0;
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for (i = 0; i < ARRAY_SIZE(s->stats_irq_count); i++) {
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s->stats_irq_count[i] = 0;
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}
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}
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static void m68k_irqc_instance_init(Object *obj)
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{
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qdev_init_gpio_in(DEVICE(obj), m68k_set_irq, M68K_IRQC_LEVEL_NUM);
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}
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static void m68k_nmi(NMIState *n, int cpu_index, Error **errp)
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{
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m68k_set_irq(n, M68K_IRQC_LEVEL_7, 1);
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}
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static const VMStateDescription vmstate_m68k_irqc = {
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.name = "m68k-irqc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT8(ipr, M68KIRQCState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property m68k_irqc_properties[] = {
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DEFINE_PROP_LINK("m68k-cpu", M68KIRQCState, cpu,
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TYPE_M68K_CPU, ArchCPU *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void m68k_irqc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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NMIClass *nc = NMI_CLASS(oc);
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InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(oc);
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device_class_set_props(dc, m68k_irqc_properties);
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nc->nmi_monitor_handler = m68k_nmi;
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dc->reset = m68k_irqc_reset;
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dc->vmsd = &vmstate_m68k_irqc;
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ic->get_statistics = m68k_irqc_get_statistics;
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ic->print_info = m68k_irqc_print_info;
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}
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static const TypeInfo m68k_irqc_type_info = {
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.name = TYPE_M68K_IRQC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(M68KIRQCState),
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.instance_init = m68k_irqc_instance_init,
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.class_init = m68k_irqc_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_NMI },
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{ TYPE_INTERRUPT_STATS_PROVIDER },
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{ }
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},
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};
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static void q800_irq_register_types(void)
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{
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type_register_static(&m68k_irqc_type_info);
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}
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type_init(q800_irq_register_types);
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