Philippe Mathieu-Daudé 0610677293 target/mips: Optimize regnames[] arrays ... Since all entries are no more than 3/4/6 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 3/4/6 const char. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-10-f4bug@amsat.org>		2021-06-24 16:48:08 +02:00
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alpha	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
arm	bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations	2021-06-16 14:33:52 +01:00
avr	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
cris	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
hexagon	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
hppa	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
i386	TCI cleanup and re-encoding	2021-06-22 10:39:16 +01:00
m68k	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
microblaze	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
mips	target/mips: Optimize regnames[] arrays	2021-06-24 16:48:08 +02:00
nios2	target/nios2: fix page-fit instruction count	2021-06-05 21:17:10 +02:00
openrisc	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
ppc	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
riscv	target/riscv: rvb: add b-ext version cpu option	2021-06-08 09:59:46 +10:00
rx	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
s390x	target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstub	2021-06-21 08:48:21 +02:00
sh4	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
sparc	docs: fix references to docs/devel/tracing.rst	2021-06-02 06:51:09 +02:00
tricore	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
xtensa	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
meson.build	Drop the deprecated unicore32 target	2021-05-12 18:20:52 +02:00