eb350d1d01
The typeof_strip_qual() is most useful for the atomic fetch-and-modify
operations in atomic.h, but it can be used elsewhere as well. For example,
QAPI_LIST_LENGTH() assumes that the argument is not const, which is not a
requirement.
Move the macro to compiler.h and, while at it, move it under #ifndef
__cplusplus to emphasize that it uses C-only constructs. A C++ version
of typeof_strip_qual() using type traits is possible[1], but beyond the
scope of this patch because the little C++ code that is in QEMU does not
use QAPI.
The patch was tested by changing the declaration of strv_from_str_list()
in qapi/qapi-type-helpers.c to:
char **strv_from_str_list(const strList *const list)
This is valid C code, and it fails to compile without this change.
[1] https://lore.kernel.org/qemu-devel/20240624205647.112034-1-flwu@google.com/
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Tested-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
285 lines
11 KiB
C
285 lines
11 KiB
C
/*
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* Simple interface for atomic operations.
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*
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* Copyright (C) 2013 Red Hat, Inc.
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*
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* Author: Paolo Bonzini <pbonzini@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* See docs/devel/atomics.rst for discussion about the guarantees each
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* atomic primitive is meant to provide.
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*/
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#ifndef QEMU_ATOMIC_H
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#define QEMU_ATOMIC_H
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#include "compiler.h"
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/* Compiler barrier */
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#define barrier() ({ asm volatile("" ::: "memory"); (void)0; })
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#ifndef __ATOMIC_RELAXED
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#error "Expecting C11 atomic ops"
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#endif
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/* Manual memory barriers
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*
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*__atomic_thread_fence does not include a compiler barrier; instead,
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* the barrier is part of __atomic_load/__atomic_store's "volatile-like"
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* semantics. If smp_wmb() is a no-op, absence of the barrier means that
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* the compiler is free to reorder stores on each side of the barrier.
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* Add one here, and similarly in smp_rmb() and smp_read_barrier_depends().
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*/
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#define smp_mb() ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); })
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#define smp_mb_release() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); })
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#define smp_mb_acquire() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); })
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/* Most compilers currently treat consume and acquire the same, but really
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* no processors except Alpha need a barrier here. Leave it in if
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* using Thread Sanitizer to avoid warnings, otherwise optimize it away.
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*/
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#ifdef QEMU_SANITIZE_THREAD
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#define smp_read_barrier_depends() ({ barrier(); __atomic_thread_fence(__ATOMIC_CONSUME); })
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#elif defined(__alpha__)
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#define smp_read_barrier_depends() asm volatile("mb":::"memory")
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#else
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#define smp_read_barrier_depends() barrier()
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#endif
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/*
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* A signal barrier forces all pending local memory ops to be observed before
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* a SIGSEGV is delivered to the *same* thread. In practice this is exactly
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* the same as barrier(), but since we have the correct builtin, use it.
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*/
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#define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST)
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/* Sanity check that the size of an atomic operation isn't "overly large".
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* Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
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* want to use them because we ought not need them, and this lets us do a
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* bit of sanity checking that other 32-bit hosts might build.
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*
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* That said, we have a problem on 64-bit ILP32 hosts in that in order to
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* sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS.
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* We'd prefer not want to pull in everything else TCG related, so handle
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* those few cases by hand.
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*
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* Note that x32 is fully detected with __x86_64__ + _ILP32, and that for
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* Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) &
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* n64 (LP64) ABIs are both detected using __mips64.
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*/
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#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64)
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# define ATOMIC_REG_SIZE 8
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#else
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# define ATOMIC_REG_SIZE sizeof(void *)
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#endif
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/* Weak atomic operations prevent the compiler moving other
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* loads/stores past the atomic operation load/store. However there is
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* no explicit memory barrier for the processor.
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*
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* The C11 memory model says that variables that are accessed from
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* different threads should at least be done with __ATOMIC_RELAXED
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* primitives or the result is undefined. Generally this has little to
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* no effect on the generated code but not using the atomic primitives
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* will get flagged by sanitizers as a violation.
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*/
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#define qatomic_read__nocheck(ptr) \
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__atomic_load_n(ptr, __ATOMIC_RELAXED)
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#define qatomic_read(ptr) \
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({ \
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qemu_build_assert(sizeof(*ptr) <= ATOMIC_REG_SIZE); \
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qatomic_read__nocheck(ptr); \
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})
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#define qatomic_set__nocheck(ptr, i) \
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__atomic_store_n(ptr, i, __ATOMIC_RELAXED)
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#define qatomic_set(ptr, i) do { \
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qemu_build_assert(sizeof(*ptr) <= ATOMIC_REG_SIZE); \
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qatomic_set__nocheck(ptr, i); \
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} while(0)
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/* See above: most compilers currently treat consume and acquire the
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* same, but this slows down qatomic_rcu_read unnecessarily.
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*/
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#ifdef QEMU_SANITIZE_THREAD
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#define qatomic_rcu_read__nocheck(ptr, valptr) \
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__atomic_load(ptr, valptr, __ATOMIC_CONSUME);
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#else
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#define qatomic_rcu_read__nocheck(ptr, valptr) \
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__atomic_load(ptr, valptr, __ATOMIC_RELAXED); \
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smp_read_barrier_depends();
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#endif
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/*
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* Preprocessor sorcery ahead: use a different identifier for the
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* local variable in each expansion, so we can nest macro calls
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* without shadowing variables.
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*/
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#define qatomic_rcu_read_internal(ptr, _val) \
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({ \
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qemu_build_assert(sizeof(*ptr) <= ATOMIC_REG_SIZE); \
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typeof_strip_qual(*ptr) _val; \
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qatomic_rcu_read__nocheck(ptr, &_val); \
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_val; \
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})
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#define qatomic_rcu_read(ptr) \
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qatomic_rcu_read_internal((ptr), MAKE_IDENTFIER(_val))
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#define qatomic_rcu_set(ptr, i) do { \
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qemu_build_assert(sizeof(*ptr) <= ATOMIC_REG_SIZE); \
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__atomic_store_n(ptr, i, __ATOMIC_RELEASE); \
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} while(0)
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#define qatomic_load_acquire(ptr) \
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({ \
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qemu_build_assert(sizeof(*ptr) <= ATOMIC_REG_SIZE); \
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typeof_strip_qual(*ptr) _val; \
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__atomic_load(ptr, &_val, __ATOMIC_ACQUIRE); \
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_val; \
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})
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#define qatomic_store_release(ptr, i) do { \
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qemu_build_assert(sizeof(*ptr) <= ATOMIC_REG_SIZE); \
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__atomic_store_n(ptr, i, __ATOMIC_RELEASE); \
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} while(0)
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/* All the remaining operations are fully sequentially consistent */
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#define qatomic_xchg__nocheck(ptr, i) ({ \
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__atomic_exchange_n(ptr, (i), __ATOMIC_SEQ_CST); \
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})
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#define qatomic_xchg(ptr, i) ({ \
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qemu_build_assert(sizeof(*ptr) <= ATOMIC_REG_SIZE); \
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qatomic_xchg__nocheck(ptr, i); \
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})
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/* Returns the old value of '*ptr' (whether the cmpxchg failed or not) */
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#define qatomic_cmpxchg__nocheck(ptr, old, new) ({ \
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typeof_strip_qual(*ptr) _old = (old); \
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(void)__atomic_compare_exchange_n(ptr, &_old, new, false, \
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__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); \
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_old; \
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})
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#define qatomic_cmpxchg(ptr, old, new) ({ \
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qemu_build_assert(sizeof(*ptr) <= ATOMIC_REG_SIZE); \
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qatomic_cmpxchg__nocheck(ptr, old, new); \
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})
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/* Provide shorter names for GCC atomic builtins, return old value */
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#define qatomic_fetch_inc(ptr) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST)
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#define qatomic_fetch_dec(ptr) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST)
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#define qatomic_fetch_add(ptr, n) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST)
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#define qatomic_fetch_sub(ptr, n) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST)
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#define qatomic_fetch_and(ptr, n) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST)
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#define qatomic_fetch_or(ptr, n) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST)
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#define qatomic_fetch_xor(ptr, n) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST)
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#define qatomic_inc_fetch(ptr) __atomic_add_fetch(ptr, 1, __ATOMIC_SEQ_CST)
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#define qatomic_dec_fetch(ptr) __atomic_sub_fetch(ptr, 1, __ATOMIC_SEQ_CST)
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#define qatomic_add_fetch(ptr, n) __atomic_add_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define qatomic_sub_fetch(ptr, n) __atomic_sub_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define qatomic_and_fetch(ptr, n) __atomic_and_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define qatomic_or_fetch(ptr, n) __atomic_or_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define qatomic_xor_fetch(ptr, n) __atomic_xor_fetch(ptr, n, __ATOMIC_SEQ_CST)
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/* And even shorter names that return void. */
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#define qatomic_inc(ptr) \
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((void) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST))
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#define qatomic_dec(ptr) \
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((void) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST))
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#define qatomic_add(ptr, n) \
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((void) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST))
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#define qatomic_sub(ptr, n) \
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((void) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST))
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#define qatomic_and(ptr, n) \
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((void) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST))
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#define qatomic_or(ptr, n) \
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((void) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST))
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#define qatomic_xor(ptr, n) \
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((void) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST))
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#define smp_wmb() smp_mb_release()
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#define smp_rmb() smp_mb_acquire()
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/*
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* SEQ_CST is weaker than the older __sync_* builtins and Linux
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* kernel read-modify-write atomics. Provide a macro to obtain
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* the same semantics.
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*/
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#if !defined(QEMU_SANITIZE_THREAD) && \
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(defined(__i386__) || defined(__x86_64__) || defined(__s390x__))
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# define smp_mb__before_rmw() signal_barrier()
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# define smp_mb__after_rmw() signal_barrier()
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#else
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# define smp_mb__before_rmw() smp_mb()
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# define smp_mb__after_rmw() smp_mb()
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#endif
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/*
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* On some architectures, qatomic_set_mb is more efficient than a store
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* plus a fence.
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*/
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#if !defined(QEMU_SANITIZE_THREAD) && \
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(defined(__i386__) || defined(__x86_64__) || defined(__s390x__))
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# define qatomic_set_mb(ptr, i) \
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({ (void)qatomic_xchg(ptr, i); smp_mb__after_rmw(); })
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#else
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# define qatomic_set_mb(ptr, i) \
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({ qatomic_store_release(ptr, i); smp_mb(); })
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#endif
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#define qatomic_fetch_inc_nonzero(ptr) ({ \
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typeof_strip_qual(*ptr) _oldn = qatomic_read(ptr); \
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while (_oldn && qatomic_cmpxchg(ptr, _oldn, _oldn + 1) != _oldn) { \
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_oldn = qatomic_read(ptr); \
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} \
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_oldn; \
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})
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/*
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* Abstractions to access atomically (i.e. "once") i64/u64 variables.
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*
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* The i386 abi is odd in that by default members are only aligned to
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* 4 bytes, which means that 8-byte types can wind up mis-aligned.
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* Clang will then warn about this, and emit a call into libatomic.
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*
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* Use of these types in structures when they will be used with atomic
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* operations can avoid this.
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*/
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typedef int64_t aligned_int64_t __attribute__((aligned(8)));
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typedef uint64_t aligned_uint64_t __attribute__((aligned(8)));
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#ifdef CONFIG_ATOMIC64
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/* Use __nocheck because sizeof(void *) might be < sizeof(u64) */
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#define qatomic_read_i64(P) \
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_Generic(*(P), int64_t: qatomic_read__nocheck(P))
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#define qatomic_read_u64(P) \
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_Generic(*(P), uint64_t: qatomic_read__nocheck(P))
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#define qatomic_set_i64(P, V) \
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_Generic(*(P), int64_t: qatomic_set__nocheck(P, V))
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#define qatomic_set_u64(P, V) \
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_Generic(*(P), uint64_t: qatomic_set__nocheck(P, V))
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static inline void qatomic64_init(void)
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{
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}
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#else /* !CONFIG_ATOMIC64 */
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int64_t qatomic_read_i64(const int64_t *ptr);
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uint64_t qatomic_read_u64(const uint64_t *ptr);
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void qatomic_set_i64(int64_t *ptr, int64_t val);
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void qatomic_set_u64(uint64_t *ptr, uint64_t val);
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void qatomic64_init(void);
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#endif /* !CONFIG_ATOMIC64 */
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#endif /* QEMU_ATOMIC_H */
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