Georg Kotheimer db9ab38b81 target/riscv: Use background registers also for MSTATUS_MPV ... The current condition for the use of background registers only considers the hypervisor load and store instructions, but not accesses from M mode via MSTATUS_MPRV+MPV. Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-03-22 21:54:40 -04:00
..
insn_trans	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
cpu_bits.h	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
cpu_helper.c	target/riscv: Use background registers also for MSTATUS_MPV	2021-03-22 21:54:40 -04:00
cpu_user.h
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	Various spelling fixes	2021-03-09 21:19:10 +01:00
cpu.h	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
csr.c	target/riscv: Make VSTIP and VSEIP read-only in hip	2021-03-22 21:54:40 -04:00
fpu_helper.c	target/riscv: fpu_helper: Match function defs in HELPER macros	2020-12-17 21:56:44 -08:00
gdbstub.c	target/riscv: Generate the GDB XML file for CSR registers dynamically	2021-01-16 10:57:21 -08:00
helper.h	target/riscv: fpu_helper: Match function defs in HELPER macros	2020-12-17 21:56:44 -08:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
machine.c	target/riscv: Add V extension state description	2020-11-03 07:17:23 -08:00
meson.build	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
monitor.c	hmp: Pass monitor to mon_get_cpu_env()	2020-11-13 12:45:51 +00:00
op_helper.c	target/riscv/pmp: Raise exception if no PMP entry is configured	2021-01-16 10:57:21 -08:00
pmp.c	target/riscv: flush TLB pages if PMP permission has been changed	2021-03-22 21:54:40 -04:00
pmp.h	target/riscv: propagate PMP permission to TLB page	2021-03-22 21:54:40 -04:00
trace-events
trace.h
translate.c	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
vector_helper.c