Philippe Mathieu-Daudé f15258b196 target/mips: Fix TX79 LQ/SQ opcodes ...

The base register address offset is *signed*.

Cc: qemu-stable@nongnu.org
Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914090447.12557-1-philmd@linaro.org>
(cherry picked from commit 18f86aecd6a1bea0f78af14587a684ad966d8d3a)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

2023-11-19 21:15:06 +03:00

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sysemu

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tcg

target/mips: Fix TX79 LQ/SQ opcodes

2023-11-19 21:15:06 +03:00

cpu-defs.c.inc

target/mips: enable GINVx support for I6400 and I6500

2023-07-10 23:33:38 +02:00

cpu-param.h

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cpu-qom.h

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cpu.c

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cpu.h

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fpu_helper.h

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fpu.c

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gdbstub.c

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helper.h

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internal.h

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Kconfig

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kvm_mips.h

kvm: Introduce kvm_arch_get_default_type hook

2023-08-24 18:43:47 +03:00

kvm.c

kvm: Introduce kvm_arch_get_default_type hook

2023-08-24 18:43:47 +03:00

meson.build

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mips-defs.h

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msa.c

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