25fa194b7b
This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
#ifndef QEMU_ARCH_INIT_H
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#define QEMU_ARCH_INIT_H
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#include "qapi/qapi-types-misc.h"
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enum {
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QEMU_ARCH_ALL = -1,
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QEMU_ARCH_ALPHA = (1 << 0),
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QEMU_ARCH_ARM = (1 << 1),
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QEMU_ARCH_CRIS = (1 << 2),
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QEMU_ARCH_I386 = (1 << 3),
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QEMU_ARCH_M68K = (1 << 4),
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QEMU_ARCH_LM32 = (1 << 5),
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QEMU_ARCH_MICROBLAZE = (1 << 6),
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QEMU_ARCH_MIPS = (1 << 7),
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QEMU_ARCH_PPC = (1 << 8),
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QEMU_ARCH_S390X = (1 << 9),
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QEMU_ARCH_SH4 = (1 << 10),
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QEMU_ARCH_SPARC = (1 << 11),
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QEMU_ARCH_XTENSA = (1 << 12),
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QEMU_ARCH_OPENRISC = (1 << 13),
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QEMU_ARCH_UNICORE32 = (1 << 14),
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QEMU_ARCH_MOXIE = (1 << 15),
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QEMU_ARCH_TRICORE = (1 << 16),
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QEMU_ARCH_NIOS2 = (1 << 17),
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QEMU_ARCH_HPPA = (1 << 18),
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QEMU_ARCH_RISCV = (1 << 19),
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};
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extern const uint32_t arch_type;
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int kvm_available(void);
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int xen_available(void);
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CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp);
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CpuModelExpansionInfo *arch_query_cpu_model_expansion(CpuModelExpansionType type,
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CpuModelInfo *mode,
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Error **errp);
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CpuModelCompareInfo *arch_query_cpu_model_comparison(CpuModelInfo *modela,
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CpuModelInfo *modelb,
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Error **errp);
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CpuModelBaselineInfo *arch_query_cpu_model_baseline(CpuModelInfo *modela,
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CpuModelInfo *modelb,
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Error **errp);
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#endif
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