Xu Lu 0eab8d42e1 target/riscv: Fix mcycle/minstret increment behavior ... The mcycle/minstret counter's stop flag is mistakenly updated on a copy on stack. Thus the counter increments even when the CY/IR bit in the mcountinhibit register is set. This commit corrects its behavior. Fixes: 3780e33732 (target/riscv: Support mcycle/minstret write operation) Signed-off-by: Xu Lu <luxu.kernel@bytedance.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> (cherry picked from commit 5cb0e7abe1) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>		2024-01-08 19:24:44 +03:00
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insn_trans	target/riscv: Fix itrigger when icount is used	2023-05-18 21:09:59 +03:00
arch_dump.c	dump: Replace opaque DumpState pointer with a typed one	2022-10-06 19:30:43 +04:00
bitmanip_helper.c	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu_bits.h	target/riscv: debug: Introduce tinfo CSR	2022-09-27 11:23:57 +10:00
cpu_helper.c	target/riscv: Honour -semihosting-config userspace=on and enable=on	2022-09-13 17:18:21 +01:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu.c	target/riscv: Convert to tcg_ops restore_state_to_opc	2022-10-26 11:11:28 +10:00
cpu.h	dump: Replace opaque DumpState pointer with a typed one	2022-10-06 19:30:43 +04:00
crypto_helper.c	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
csr.c	target/riscv: Fix mcycle/minstret increment behavior	2024-01-08 19:24:44 +03:00
debug.c	target/riscv: debug: Add initial support of type 6 trigger	2022-09-27 11:23:57 +10:00
debug.h	target/riscv: debug: Add initial support of type 6 trigger	2022-09-27 11:23:57 +10:00
fpu_helper.c	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
gdbstub.c	target/riscv: Check the correct exception cause in vector GDB stub	2022-09-27 07:04:38 +10:00
helper.h	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
insn16.decode	target/riscv: fix shifts shamt value for rv128c	2022-09-07 09:18:32 +02:00
insn32.decode	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: rvv: Add mask agnostic for vv instructions	2022-09-07 09:18:32 +02:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
kvm_riscv.h	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm-stub.c	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm.c	kvm: Introduce kvm_arch_get_default_type hook	2023-09-11 10:53:50 +03:00
m128_helper.c	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
machine.c	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	2022-09-27 11:23:57 +10:00
meson.build	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
monitor.c	target/riscv: Fix incorrect PTE merge in walk_pte	2022-04-29 10:47:46 +10:00
op_helper.c	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
pmp.c	target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes	2023-09-13 12:21:22 +03:00
pmp.h	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
pmu.c	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
pmu.h	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h	Clean up ill-advised or unusual header guards	2022-05-11 16:50:01 +02:00
time_helper.c	target/riscv: Add vstimecmp support	2022-09-07 09:19:15 +02:00
time_helper.h	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Set pc_succ_insn for !rvc illegal insn	2023-03-29 10:20:04 +03:00
vector_helper.c	treewide: Remove the unnecessary space before semicolon	2022-10-24 13:41:10 +02:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00