716 lines
27 KiB
C
716 lines
27 KiB
C
/*
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* x86 SVM helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "exec/cpu-all.h"
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#include "helper.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "exec/softmmu_exec.h"
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#endif /* !defined(CONFIG_USER_ONLY) */
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/* Secure Virtual Machine helpers */
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#if defined(CONFIG_USER_ONLY)
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void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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{
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}
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void helper_vmmcall(CPUX86State *env)
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{
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}
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void helper_vmload(CPUX86State *env, int aflag)
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{
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}
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void helper_vmsave(CPUX86State *env, int aflag)
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{
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}
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void helper_stgi(CPUX86State *env)
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{
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}
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void helper_clgi(CPUX86State *env)
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{
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}
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void helper_skinit(CPUX86State *env)
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{
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}
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void helper_invlpga(CPUX86State *env, int aflag)
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{
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}
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void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
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{
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}
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void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1)
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{
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}
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void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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uint64_t param)
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{
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}
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void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,
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uint64_t param)
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{
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}
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void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
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uint32_t next_eip_addend)
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{
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}
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#else
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static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
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const SegmentCache *sc)
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{
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stw_phys(addr + offsetof(struct vmcb_seg, selector),
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sc->selector);
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stq_phys(addr + offsetof(struct vmcb_seg, base),
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sc->base);
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stl_phys(addr + offsetof(struct vmcb_seg, limit),
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sc->limit);
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stw_phys(addr + offsetof(struct vmcb_seg, attrib),
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((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
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}
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static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
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SegmentCache *sc)
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{
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unsigned int flags;
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sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector));
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sc->base = ldq_phys(addr + offsetof(struct vmcb_seg, base));
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sc->limit = ldl_phys(addr + offsetof(struct vmcb_seg, limit));
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flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib));
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sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
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}
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static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
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int seg_reg)
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{
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SegmentCache sc1, *sc = &sc1;
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svm_load_seg(env, addr, sc);
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cpu_x86_load_seg_cache(env, seg_reg, sc->selector,
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sc->base, sc->limit, sc->flags);
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}
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void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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{
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target_ulong addr;
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uint32_t event_inj;
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uint32_t int_ctl;
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0);
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if (aflag == 2) {
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addr = EAX;
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} else {
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addr = (uint32_t)EAX;
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}
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmrun! " TARGET_FMT_lx "\n", addr);
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env->vm_vmcb = addr;
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/* save the current CPU state in the hsave page */
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base),
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env->gdt.base);
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stl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit),
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env->gdt.limit);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.base),
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env->idt.base);
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stl_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.limit),
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env->idt.limit);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr0), env->cr[0]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr2), env->cr[2]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr3), env->cr[3]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.cr4), env->cr[4]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6), env->dr[6]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7), env->dr[7]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.efer), env->efer);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rflags),
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cpu_compute_eflags(env));
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.es),
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&env->segs[R_ES]);
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.cs),
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&env->segs[R_CS]);
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ss),
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&env->segs[R_SS]);
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
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&env->segs[R_DS]);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip),
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EIP + next_eip_addend);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp), ESP);
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stq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax), EAX);
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/* load the interception bitmaps so we do not need to access the
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vmcb in svm mode */
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env->intercept = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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control.intercept));
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env->intercept_cr_read = lduw_phys(env->vm_vmcb +
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offsetof(struct vmcb,
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control.intercept_cr_read));
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env->intercept_cr_write = lduw_phys(env->vm_vmcb +
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offsetof(struct vmcb,
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control.intercept_cr_write));
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env->intercept_dr_read = lduw_phys(env->vm_vmcb +
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offsetof(struct vmcb,
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control.intercept_dr_read));
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env->intercept_dr_write = lduw_phys(env->vm_vmcb +
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offsetof(struct vmcb,
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control.intercept_dr_write));
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env->intercept_exceptions = ldl_phys(env->vm_vmcb +
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offsetof(struct vmcb,
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control.intercept_exceptions
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));
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/* enable intercepts */
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env->hflags |= HF_SVMI_MASK;
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env->tsc_offset = ldq_phys(env->vm_vmcb +
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offsetof(struct vmcb, control.tsc_offset));
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env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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save.gdtr.base));
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env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
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save.gdtr.limit));
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env->idt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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save.idtr.base));
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env->idt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
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save.idtr.limit));
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/* clear exit_info_2 so we behave like the real hardware */
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stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0);
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cpu_x86_update_cr0(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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save.cr0)));
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cpu_x86_update_cr4(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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save.cr4)));
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cpu_x86_update_cr3(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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save.cr3)));
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env->cr[2] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2));
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int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
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env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK);
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if (int_ctl & V_INTR_MASKING_MASK) {
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env->v_tpr = int_ctl & V_TPR_MASK;
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env->hflags2 |= HF2_VINTR_MASK;
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if (env->eflags & IF_MASK) {
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env->hflags2 |= HF2_HIF_MASK;
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}
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}
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cpu_load_efer(env,
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ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer)));
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env->eflags = 0;
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cpu_load_eflags(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
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save.rflags)),
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~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
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CC_OP = CC_OP_EFLAGS;
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.es),
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R_ES);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.cs),
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R_CS);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ss),
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R_SS);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
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R_DS);
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EIP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip));
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env->eip = EIP;
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ESP = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp));
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EAX = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax));
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env->dr[7] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7));
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env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
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cpu_x86_set_cpl(env, ldub_phys(env->vm_vmcb + offsetof(struct vmcb,
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save.cpl)));
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/* FIXME: guest state consistency checks */
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switch (ldub_phys(env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
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case TLB_CONTROL_DO_NOTHING:
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break;
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case TLB_CONTROL_FLUSH_ALL_ASID:
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/* FIXME: this is not 100% correct but should work for now */
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tlb_flush(env, 1);
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break;
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}
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env->hflags2 |= HF2_GIF_MASK;
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if (int_ctl & V_IRQ_MASK) {
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env->interrupt_request |= CPU_INTERRUPT_VIRQ;
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}
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/* maybe we need to inject an event */
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event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
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control.event_inj));
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if (event_inj & SVM_EVTINJ_VALID) {
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uint8_t vector = event_inj & SVM_EVTINJ_VEC_MASK;
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uint16_t valid_err = event_inj & SVM_EVTINJ_VALID_ERR;
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uint32_t event_inj_err = ldl_phys(env->vm_vmcb +
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offsetof(struct vmcb,
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control.event_inj_err));
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "Injecting(%#hx): ", valid_err);
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/* FIXME: need to implement valid_err */
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switch (event_inj & SVM_EVTINJ_TYPE_MASK) {
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case SVM_EVTINJ_TYPE_INTR:
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env->exception_index = vector;
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env->error_code = event_inj_err;
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env->exception_is_int = 0;
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env->exception_next_eip = -1;
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "INTR");
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/* XXX: is it always correct? */
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do_interrupt_x86_hardirq(env, vector, 1);
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break;
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case SVM_EVTINJ_TYPE_NMI:
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env->exception_index = EXCP02_NMI;
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env->error_code = event_inj_err;
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env->exception_is_int = 0;
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env->exception_next_eip = EIP;
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI");
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cpu_loop_exit(env);
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break;
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case SVM_EVTINJ_TYPE_EXEPT:
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env->exception_index = vector;
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env->error_code = event_inj_err;
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env->exception_is_int = 0;
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env->exception_next_eip = -1;
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT");
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cpu_loop_exit(env);
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break;
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case SVM_EVTINJ_TYPE_SOFT:
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env->exception_index = vector;
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env->error_code = event_inj_err;
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env->exception_is_int = 1;
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env->exception_next_eip = EIP;
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT");
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cpu_loop_exit(env);
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break;
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}
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qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", env->exception_index,
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env->error_code);
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}
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}
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void helper_vmmcall(CPUX86State *env)
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{
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMMCALL, 0);
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raise_exception(env, EXCP06_ILLOP);
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}
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void helper_vmload(CPUX86State *env, int aflag)
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{
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target_ulong addr;
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0);
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if (aflag == 2) {
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addr = EAX;
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} else {
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addr = (uint32_t)EAX;
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}
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx
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"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
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addr, ldq_phys(addr + offsetof(struct vmcb,
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save.fs.base)),
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env->segs[R_FS].base);
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svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.fs), R_FS);
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svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.gs), R_GS);
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svm_load_seg(env, addr + offsetof(struct vmcb, save.tr), &env->tr);
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svm_load_seg(env, addr + offsetof(struct vmcb, save.ldtr), &env->ldt);
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#ifdef TARGET_X86_64
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env->kernelgsbase = ldq_phys(addr + offsetof(struct vmcb,
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save.kernel_gs_base));
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env->lstar = ldq_phys(addr + offsetof(struct vmcb, save.lstar));
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env->cstar = ldq_phys(addr + offsetof(struct vmcb, save.cstar));
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env->fmask = ldq_phys(addr + offsetof(struct vmcb, save.sfmask));
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#endif
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env->star = ldq_phys(addr + offsetof(struct vmcb, save.star));
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env->sysenter_cs = ldq_phys(addr + offsetof(struct vmcb, save.sysenter_cs));
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env->sysenter_esp = ldq_phys(addr + offsetof(struct vmcb,
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save.sysenter_esp));
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env->sysenter_eip = ldq_phys(addr + offsetof(struct vmcb,
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save.sysenter_eip));
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}
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void helper_vmsave(CPUX86State *env, int aflag)
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{
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target_ulong addr;
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0);
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if (aflag == 2) {
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addr = EAX;
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} else {
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addr = (uint32_t)EAX;
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}
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx
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"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
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addr, ldq_phys(addr + offsetof(struct vmcb, save.fs.base)),
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env->segs[R_FS].base);
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svm_save_seg(env, addr + offsetof(struct vmcb, save.fs),
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&env->segs[R_FS]);
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svm_save_seg(env, addr + offsetof(struct vmcb, save.gs),
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&env->segs[R_GS]);
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svm_save_seg(env, addr + offsetof(struct vmcb, save.tr),
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&env->tr);
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svm_save_seg(env, addr + offsetof(struct vmcb, save.ldtr),
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&env->ldt);
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#ifdef TARGET_X86_64
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stq_phys(addr + offsetof(struct vmcb, save.kernel_gs_base),
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env->kernelgsbase);
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stq_phys(addr + offsetof(struct vmcb, save.lstar), env->lstar);
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stq_phys(addr + offsetof(struct vmcb, save.cstar), env->cstar);
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stq_phys(addr + offsetof(struct vmcb, save.sfmask), env->fmask);
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#endif
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stq_phys(addr + offsetof(struct vmcb, save.star), env->star);
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stq_phys(addr + offsetof(struct vmcb, save.sysenter_cs), env->sysenter_cs);
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stq_phys(addr + offsetof(struct vmcb, save.sysenter_esp),
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env->sysenter_esp);
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stq_phys(addr + offsetof(struct vmcb, save.sysenter_eip),
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env->sysenter_eip);
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}
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void helper_stgi(CPUX86State *env)
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{
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cpu_svm_check_intercept_param(env, SVM_EXIT_STGI, 0);
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env->hflags2 |= HF2_GIF_MASK;
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}
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void helper_clgi(CPUX86State *env)
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{
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cpu_svm_check_intercept_param(env, SVM_EXIT_CLGI, 0);
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env->hflags2 &= ~HF2_GIF_MASK;
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}
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void helper_skinit(CPUX86State *env)
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{
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cpu_svm_check_intercept_param(env, SVM_EXIT_SKINIT, 0);
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/* XXX: not implemented */
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raise_exception(env, EXCP06_ILLOP);
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}
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void helper_invlpga(CPUX86State *env, int aflag)
|
|
{
|
|
target_ulong addr;
|
|
|
|
cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0);
|
|
|
|
if (aflag == 2) {
|
|
addr = EAX;
|
|
} else {
|
|
addr = (uint32_t)EAX;
|
|
}
|
|
|
|
/* XXX: could use the ASID to see if it is needed to do the
|
|
flush */
|
|
tlb_flush_page(env, addr);
|
|
}
|
|
|
|
void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
|
|
uint64_t param)
|
|
{
|
|
if (likely(!(env->hflags & HF_SVMI_MASK))) {
|
|
return;
|
|
}
|
|
switch (type) {
|
|
case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR0 + 8:
|
|
if (env->intercept_cr_read & (1 << (type - SVM_EXIT_READ_CR0))) {
|
|
helper_vmexit(env, type, param);
|
|
}
|
|
break;
|
|
case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR0 + 8:
|
|
if (env->intercept_cr_write & (1 << (type - SVM_EXIT_WRITE_CR0))) {
|
|
helper_vmexit(env, type, param);
|
|
}
|
|
break;
|
|
case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR0 + 7:
|
|
if (env->intercept_dr_read & (1 << (type - SVM_EXIT_READ_DR0))) {
|
|
helper_vmexit(env, type, param);
|
|
}
|
|
break;
|
|
case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR0 + 7:
|
|
if (env->intercept_dr_write & (1 << (type - SVM_EXIT_WRITE_DR0))) {
|
|
helper_vmexit(env, type, param);
|
|
}
|
|
break;
|
|
case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 31:
|
|
if (env->intercept_exceptions & (1 << (type - SVM_EXIT_EXCP_BASE))) {
|
|
helper_vmexit(env, type, param);
|
|
}
|
|
break;
|
|
case SVM_EXIT_MSR:
|
|
if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) {
|
|
/* FIXME: this should be read in at vmrun (faster this way?) */
|
|
uint64_t addr = ldq_phys(env->vm_vmcb +
|
|
offsetof(struct vmcb,
|
|
control.msrpm_base_pa));
|
|
uint32_t t0, t1;
|
|
|
|
switch ((uint32_t)ECX) {
|
|
case 0 ... 0x1fff:
|
|
t0 = (ECX * 2) % 8;
|
|
t1 = (ECX * 2) / 8;
|
|
break;
|
|
case 0xc0000000 ... 0xc0001fff:
|
|
t0 = (8192 + ECX - 0xc0000000) * 2;
|
|
t1 = (t0 / 8);
|
|
t0 %= 8;
|
|
break;
|
|
case 0xc0010000 ... 0xc0011fff:
|
|
t0 = (16384 + ECX - 0xc0010000) * 2;
|
|
t1 = (t0 / 8);
|
|
t0 %= 8;
|
|
break;
|
|
default:
|
|
helper_vmexit(env, type, param);
|
|
t0 = 0;
|
|
t1 = 0;
|
|
break;
|
|
}
|
|
if (ldub_phys(addr + t1) & ((1 << param) << t0)) {
|
|
helper_vmexit(env, type, param);
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
if (env->intercept & (1ULL << (type - SVM_EXIT_INTR))) {
|
|
helper_vmexit(env, type, param);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,
|
|
uint64_t param)
|
|
{
|
|
helper_svm_check_intercept_param(env, type, param);
|
|
}
|
|
|
|
void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
|
|
uint32_t next_eip_addend)
|
|
{
|
|
if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) {
|
|
/* FIXME: this should be read in at vmrun (faster this way?) */
|
|
uint64_t addr = ldq_phys(env->vm_vmcb +
|
|
offsetof(struct vmcb, control.iopm_base_pa));
|
|
uint16_t mask = (1 << ((param >> 4) & 7)) - 1;
|
|
|
|
if (lduw_phys(addr + port / 8) & (mask << (port & 7))) {
|
|
/* next EIP */
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
|
|
env->eip + next_eip_addend);
|
|
helper_vmexit(env, SVM_EXIT_IOIO, param | (port << 16));
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Note: currently only 32 bits of exit_code are used */
|
|
void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
|
|
{
|
|
uint32_t int_ctl;
|
|
|
|
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016"
|
|
PRIx64 ", " TARGET_FMT_lx ")!\n",
|
|
exit_code, exit_info_1,
|
|
ldq_phys(env->vm_vmcb + offsetof(struct vmcb,
|
|
control.exit_info_2)),
|
|
EIP);
|
|
|
|
if (env->hflags & HF_INHIBIT_IRQ_MASK) {
|
|
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state),
|
|
SVM_INTERRUPT_SHADOW_MASK);
|
|
env->hflags &= ~HF_INHIBIT_IRQ_MASK;
|
|
} else {
|
|
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0);
|
|
}
|
|
|
|
/* Save the VM state in the vmcb */
|
|
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.es),
|
|
&env->segs[R_ES]);
|
|
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.cs),
|
|
&env->segs[R_CS]);
|
|
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ss),
|
|
&env->segs[R_SS]);
|
|
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
|
|
&env->segs[R_DS]);
|
|
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base),
|
|
env->gdt.base);
|
|
stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit),
|
|
env->gdt.limit);
|
|
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.base),
|
|
env->idt.base);
|
|
stl_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit),
|
|
env->idt.limit);
|
|
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.efer), env->efer);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr0), env->cr[0]);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2), env->cr[2]);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]);
|
|
|
|
int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
|
|
int_ctl &= ~(V_TPR_MASK | V_IRQ_MASK);
|
|
int_ctl |= env->v_tpr & V_TPR_MASK;
|
|
if (env->interrupt_request & CPU_INTERRUPT_VIRQ) {
|
|
int_ctl |= V_IRQ_MASK;
|
|
}
|
|
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl);
|
|
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rflags),
|
|
cpu_compute_eflags(env));
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rip),
|
|
env->eip);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rsp), ESP);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.rax), EAX);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]);
|
|
stb_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl),
|
|
env->hflags & HF_CPL_MASK);
|
|
|
|
/* Reload the host state from vm_hsave */
|
|
env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK);
|
|
env->hflags &= ~HF_SVMI_MASK;
|
|
env->intercept = 0;
|
|
env->intercept_exceptions = 0;
|
|
env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
|
|
env->tsc_offset = 0;
|
|
|
|
env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
|
|
save.gdtr.base));
|
|
env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb,
|
|
save.gdtr.limit));
|
|
|
|
env->idt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
|
|
save.idtr.base));
|
|
env->idt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb,
|
|
save.idtr.limit));
|
|
|
|
cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
|
|
save.cr0)) |
|
|
CR0_PE_MASK);
|
|
cpu_x86_update_cr4(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
|
|
save.cr4)));
|
|
cpu_x86_update_cr3(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
|
|
save.cr3)));
|
|
/* we need to set the efer after the crs so the hidden flags get
|
|
set properly */
|
|
cpu_load_efer(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
|
|
save.efer)));
|
|
env->eflags = 0;
|
|
cpu_load_eflags(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb,
|
|
save.rflags)),
|
|
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
|
|
CC_OP = CC_OP_EFLAGS;
|
|
|
|
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.es),
|
|
R_ES);
|
|
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.cs),
|
|
R_CS);
|
|
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ss),
|
|
R_SS);
|
|
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
|
|
R_DS);
|
|
|
|
EIP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
|
|
ESP = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
|
|
EAX = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
|
|
|
|
env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
|
|
env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));
|
|
|
|
/* other setups */
|
|
cpu_x86_set_cpl(env, 0);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_code),
|
|
exit_code);
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_1),
|
|
exit_info_1);
|
|
|
|
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info),
|
|
ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
|
|
control.event_inj)));
|
|
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err),
|
|
ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
|
|
control.event_inj_err)));
|
|
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0);
|
|
|
|
env->hflags2 &= ~HF2_GIF_MASK;
|
|
/* FIXME: Resets the current ASID register to zero (host ASID). */
|
|
|
|
/* Clears the V_IRQ and V_INTR_MASKING bits inside the processor. */
|
|
|
|
/* Clears the TSC_OFFSET inside the processor. */
|
|
|
|
/* If the host is in PAE mode, the processor reloads the host's PDPEs
|
|
from the page table indicated the host's CR3. If the PDPEs contain
|
|
illegal state, the processor causes a shutdown. */
|
|
|
|
/* Forces CR0.PE = 1, RFLAGS.VM = 0. */
|
|
env->cr[0] |= CR0_PE_MASK;
|
|
env->eflags &= ~VM_MASK;
|
|
|
|
/* Disables all breakpoints in the host DR7 register. */
|
|
|
|
/* Checks the reloaded host state for consistency. */
|
|
|
|
/* If the host's rIP reloaded by #VMEXIT is outside the limit of the
|
|
host's code segment or non-canonical (in the case of long mode), a
|
|
#GP fault is delivered inside the host. */
|
|
|
|
/* remove any pending exception */
|
|
env->exception_index = -1;
|
|
env->error_code = 0;
|
|
env->old_exception = -1;
|
|
|
|
cpu_loop_exit(env);
|
|
}
|
|
|
|
void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
|
|
{
|
|
helper_vmexit(env, exit_code, exit_info_1);
|
|
}
|
|
|
|
#endif
|